Petri-net based scheduling strategy for semiconductor manufacturing processes

Chemical Engineering Research and Design

Volumn 89, Issue 3, 2011, Pages 291-300

  Lee, Yin Hsuan ^a   Chang, Chuei Tin ^a   Wong, David Shan Hill ^b   Jang, Shi Shang ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

MILP; MINLP; Petri net; Scheduling; Semiconductor

Indexed keywords

BATCH CHEMICAL PROCESS; ETCHING PROCESS; FLOW PROCESS; HUMAN ERRORS; INDUSTRIAL PROCESSS; MATHEMATICAL PROGRAMMING MODELS; MILP; MINLP; OPERATIONAL EFFICIENCIES; OPTIMAL SCHEDULE; PROCESS FLOWS; PRODUCTION SCHEDULING; SCHEDULING MODELS; SCHEDULING STRATEGIES; SEMICONDUCTOR; SEMICONDUCTOR MANUFACTURING; SEMICONDUCTOR MANUFACTURING PROCESS; SEMICONDUCTOR PROCESS; TEST PROCESS; WAFER PROCESSING;

ERRORS; GRAPH THEORY; MANUFACTURE; MATHEMATICAL PROGRAMMING; PETRI NETS; PHOTOLITHOGRAPHY; PRODUCTION ENGINEERING; SCHEDULING; SEMICONDUCTOR DEVICE MANUFACTURE; SYSTEMATIC ERRORS;

SCHEDULING ALGORITHMS;

EID: 79952002537     PISSN: 02638762     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.cherd.2010.07.005     Document Type: Article

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