Modeling, qualitative analysis, and performance evaluation of the etching area in an IC wafer fabrication system using petri nets

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 3, 1998, Pages 358-373

  Jeng, Mu Der ^a,c   Xie, Xiaolan ^b,c   Chou, Shih Wei ^a  

^a NATIONAL TAIWAN OCEAN UNIVERSITY   (Taiwan)

^b INRIA/MACSI Team   (France)

^c IEEE   (Taiwan)

Author keywords

Discrete event systems; Modules; Semiconductor manufacturing; Synthesis

Indexed keywords

COMPUTER SIMULATION; DISCRETE TIME CONTROL SYSTEMS; ETCHING; PETRI NETS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS;

INTEGRATED CIRCUIT WAFER FABRICATION SYSTEM;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0032137582     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.705371     Document Type: Review

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