Many-thread aware prefetching mechanisms for GPGPU applications

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 213-224

  Lee, Jaekyu ^a   Lakshminarayana, Nagesh B ^a   Kim, Hyesoon ^a   Vuduc, Richard ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

GPGPU; Prefetch throttling; Prefetching

Indexed keywords

CPU SYSTEMS; GPGPU; HARDWARE AND SOFTWARE; MEMORY ACCESS; MEMORY LATENCIES; MULTITHREADED; PERFORMANCE BENEFITS; PREFETCH THROTTLING; PREFETCHES; PREFETCHING; THREAD LEVEL PARALLELISM; TRAINING ALGORITHMS;

HARDWARE;

PROGRAM PROCESSORS;

EID: 79951719035     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.44     Document Type: Conference Paper

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