Resource-aware compiler prefetching for many-cores

9th International Symposium on Parallel and Distributed Computing, ISPDC 2010

Volumn , Issue , 2010, Pages 133-140

  Caragea, George C ^a   Tzannes, Alexandros ^a   Keceli, Fuat ^a   Barua, Rajeev ^a   Vishkin, Uzi ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Optimizing compilers; Parallel architectures

Indexed keywords

CACHE HIERARCHIES; CACHE MISS; COMPILER ALGORITHMS; HARDWARE AND SOFTWARE; MANY-CORE ARCHITECTURE; MEMORY LEVEL PARALLELISMS; OPTIMIZING COMPILERS; OUT-OF-ORDER PROCESSORS; PREFETCHES; PREFETCHING; PREFETCHING ALGORITHM; RESOURCE AWARE; STATE OF THE ART;

BUFFER STORAGE; OPTIMIZATION; PARALLEL ARCHITECTURES; PROGRAM COMPILERS;

ALGORITHMS;

EID: 77956435385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPDC.2010.16     Document Type: Conference Paper

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