메뉴 건너뛰기




Volumn 7, Issue 1, 2011, Pages 152-159

Bandwidth-aware application mapping for NoC-based MPSoCs

Author keywords

Ant colony optimization; Bandwidth; Mapping; Network on chip

Indexed keywords

ANT-COLONY OPTIMIZATION; APPLICATION MAPPING; APPLICATION TASKS; BANDWIDTH REQUIREMENT; BANDWIDTH-AWARE; MAPPING METHOD; MULTI-PROCESSORS; NETWORK ON CHIP; NOC ARCHITECTURES; ON CHIPS; POWER CONSUMPTION; SIMULATION RESULT; STATE-OF-ART METHODS;

EID: 79551650533     PISSN: 15539105     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (40)

References (18)
  • 1
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • Las Vegas, USA, June 18-22
    • Dally, J. W., and Towles, B.: 'Route packets, not wires: on-chip interconnection networks'. In Proceedings of the 38th Design Automation Conference (DAC), Las Vegas, USA, June 18-22, 2001, pp. 684-689.
    • (2001) Proceedings of the 38th Design Automation Conference (DAC) , pp. 684-689
    • Dally, J.W.1    Towles, B.2
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new soc paradigm
    • Jan.
    • Benini, L., and Micheli, D. G.: 'Networks on chips: a new soc paradigm'. Computer, Jan. 2002. vol. 35, no. 1, pp. 70-78.
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    Micheli, D.G.2
  • 4
    • 33751400283 scopus 로고    scopus 로고
    • NoCEE: Energy macro-model extraction methodology for network on chip routers
    • Nov.
    • Chan, J., and Parameswaran, S.: 'NoCEE: Energy macro-model extraction methodology for network on chip routers'. in Proc. Int. Conf. Comput.-Aided Des., Nov. 2005, pp. 254-259.
    • (2005) Proc. Int. Conf. Comput.-Aided Des. , pp. 254-259
    • Chan, J.1    Parameswaran, S.2
  • 5
    • 3042565282 scopus 로고    scopus 로고
    • A power and performance model for network-on-chip architectures
    • Feb.
    • Banerjee, N., Vellank, P., and Chatha, S. K.: 'A power and performance model for network-on-chip architectures'. in Proc. Des., Autom. Test Eur. Conf., Feb. 2004, pp. 1250-1255.
    • (2004) Proc. Des., Autom. Test Eur. Conf. , pp. 1250-1255
    • Banerjee, N.1    Vellank, P.2    Chatha, S.K.3
  • 6
    • 84954421164 scopus 로고    scopus 로고
    • Energy-aware mapping for tile-based noc architectures under performance constraints
    • September 1-6
    • J. Hu and R. Marculescu. "Energy-aware mapping for tile-based noc architectures under performance constraints". Asia and South Pacific Design Automation Conference, September 1-6, 2003, pp: 53-57.
    • (2003) Asia and South Pacific Design Automation Conference , pp. 53-57
    • Hu, J.1    Marculescu, R.2
  • 7
    • 84893760422 scopus 로고    scopus 로고
    • Exploiting the routing flexibility for energy/performance aware mapping for regular noc architectures
    • September 1-6
    • J. Hu and R. Marculescu. "Exploiting the routing flexibility for energy/performance aware mapping for regular noc architectures". Proceedings Design, Autimation and Test in Europe, September 1-6, 2003. pp: 688-693.
    • (2003) Proceedings Design, Autimation and Test in Europe , pp. 688-693
    • Hu, J.1    Marculescu, R.2
  • 8
    • 3042567207 scopus 로고    scopus 로고
    • Bandwidth-constrained mapping of cores onto noc architectures
    • February 16-20, 2004. Paris, France
    • S. Murali and G. Micheli. "Bandwidth-constrained mapping of cores onto noc architectures". Proceeding Design, Automation and Test in Europe, 2004. February 16-20, 2004. Paris, France. pp: 896-901.
    • (2004) Proceeding Design, Automation and Test in Europe , pp. 896-901
    • Murali, S.1    Micheli, G.2
  • 9
    • 84944322013 scopus 로고    scopus 로고
    • A two-step genetic algorithm for mapping task graphs to a network-on-chip architecture
    • September 1-6, Belek-Antalya, Turkey
    • T. Lei and S. Kumar. "A two-step genetic algorithm for mapping task graphs to a network-on-chip architecture". Euromicro Symposium on Digital Systems Design, September 1-6, 2003. Belek-Antalya, Turkey. pp: 53-57.
    • (2003) Euromicro Symposium on Digital Systems Design , pp. 53-57
    • Lei, T.1    Kumar, S.2
  • 11
    • 34047189354 scopus 로고    scopus 로고
    • Efficient link capacity and qos design for network-on-chip
    • Munich, Germany. March 6-10
    • Guz, Z., Walter, I., and Bolotin, E.: 'Efficient link capacity and qos design for network-on-chip'. Design, Automation and Test in Europe, 2006. Munich, Germany. March 6-10, 2006. pp. 1-6.
    • (2006) Design, Automation and Test in Europe , pp. 1-6
    • Guz, Z.1    Walter, I.2    Bolotin, E.3
  • 12
    • 0002529867 scopus 로고    scopus 로고
    • ACO algorithms for the quadratic assignment problem
    • T. Stutzle and M. Dorigo. ACO algorithms for the quadratic assignment problem. New ideas in optimization, pp: 33-50, 1999.
    • (1999) New Ideas in Optimization , pp. 33-50
    • Stutzle, T.1    Dorigo, M.2
  • 13
    • 84948696213 scopus 로고    scopus 로고
    • A network on chip architecture and design methodology
    • April
    • S. Kumar., A. Jantsch., and J.-P. Soininen, etc. "A network on chip architecture and design methodology", Proc. Symposium on VLSI. April 2002. pp. 117-124.
    • (2002) Proc. Symposium on VLSI , pp. 117-124
    • Kumar, S.1    Jantsch, A.2    Soininen, J.-P.3
  • 14
    • 84943681390 scopus 로고
    • A survey of wormhole routing techniques in direct networks
    • Feb.
    • Ni, M. L., and McKinley, K. P.: 'A survey of wormhole routing techniques in direct networks'. Computer, Feb. 1993. vol. 26, no. 2, pp. 62-76.
    • (1993) Computer , vol.26 , Issue.2 , pp. 62-76
    • Ni, M.L.1    McKinley, K.P.2
  • 17
    • 0036030760 scopus 로고    scopus 로고
    • Mapping of MPEG4 decoding on a flexible architecture platform
    • Jan.
    • Vander, T. B. E., and Jaspers, T. G. E.: 'Mapping of MPEG4 decoding on a flexible architecture platform'. SPIE 2002, Jan. 2002, pp. 1-13.
    • (2002) SPIE 2002 , pp. 1-13
    • Vander, T.B.E.1    Jaspers, T.G.E.2
  • 18
    • 14844365666 scopus 로고    scopus 로고
    • NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
    • Bertozzi, D., Jalabert, A., and Murali, S., et al.: 'NoC synthesis flow for customized domain specific multiprocessor systems-on-chip'. IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, 2005.
    • (2005) IEEE Transactions on Parallel and Distributed Systems , vol.16 , Issue.2 , pp. 113-129
    • Bertozzi, D.1    Jalabert, A.2    Murali, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.