A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 236-247

  Chae, Youngcheol ^a   Cheon, Jimin ^b   Lim, Seunghyun ^b   Kwon, Minho ^b   Yoo, Kwisung ^b   Jung, Wunki ^b   Lee, Dong Hun ^b   Ham, Seogheon ^b   Han, Gunhee ^a  

^a Yonsei University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

CMOS image sensor; column parallel delta sigma ( ) ADC; high speed; low noise and wide dynamic range; second order ADC

Indexed keywords

CMOS IMAGE SENSOR; DELTA-SIGMA; HIGH SPEED; LOW NOISE; SECOND ORDERS;

BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; DIGITAL CAMERAS; ENERGY EFFICIENCY; IMAGE SENSORS; PIXELS;

ANALOG TO DIGITAL CONVERSION;

EID: 78650918995     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2085910     Document Type: Conference Paper

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