A 0.1e- Vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 268-270

  Park, Jong Ho ^a   Aoyama, Satoshi ^a   Watanabe, Takashi ^a   Akahori, Tomoyuki ^a   Kosugi, Tomohiko ^a   Isobe, Keigo ^a   Kaneko, Yuichi ^a   Liu, Zheng ^a   Muramatsu, Kazuki ^a   Matsuyama, Takeshi ^a   Kawahito, Shoji ^a,b  

^a 10F   (Japan)

^b SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349268242     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977411     Document Type: Conference Paper

References (4)

1. S. Yoshihara et al., "A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change," ISSCC Dig. Tech Papers, pp. 492-493, Feb. 2006.
2. Y. Nitta et al., "High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor," ISSCC Dig. Tech Papers, pp. 500-501, Feb. 2006.
3. S. Matsuo et al., "A Very Low Column FPN and Row Temporal Noise 8.9 M-Pixel, 60 fps CMOS Image Sensor with 14bit Column Parallel SA- ADC," IEEE Symp. VLSI Circuits, pp. 138-139, June 2008.
4. S. Kawahito et al., "A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits," ISSCC Dig. Tech Papers, pp. 56-57, Feb. 2008.