8.9-megapixel video image sensor with 14-b column-parallel SA-ADC

IEEE Transactions on Electron Devices

Volumn 56, Issue 11, 2009, Pages 2380-2389

  Matsuo, Shinichiro ^a   Bales, Timothy J ^b   Shoda, Masahiro ^a   Osawa, Shinji ^a   Kawamura, Katsuyuki ^a   Andersson, Anders ^a   Haque, Munirul ^a   Honda, Hidenari ^a   Almond, Byran ^b   Mo, Yaowu ^c   Gleason, Jeffrey ^c   Chow, Tony ^c   Takayanagi, Isao ^a  

^a Aptina Japan LLC   (Japan)

^b Aptina UK Ltd   (United Kingdom)

^c Aptina LLC   (United States)

Author keywords

CMOS image sensor; Column parallel processing; Digital column processor; High resolution; High sensitivity; Low readout noise; Low structural noise; Successive approximation analog to digital converter (SA ADC)

Indexed keywords

CMOS IMAGE SENSOR; COLUMN-PARALLEL PROCESSING; DIGITAL COLUMN PROCESSOR; HIGH RESOLUTION; HIGH SENSITIVITY; LOW READOUT NOISE; LOW STRUCTURAL NOISE; SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (SA-ADC);

APPROXIMATION THEORY; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; FREQUENCY CONVERTERS; IMAGE SENSORS; MULTICARRIER MODULATION; PIXELS; SIMULATED ANNEALING; SOLID-STATE SENSORS;

COMPUTER GRAPHICS;

EID: 70350738557     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2030649     Document Type: Article

References (21)

1. K. Mitani, M. Sugawara, and F. Okano, "Experimental ultra-high-definition color camera system with three 8 M-pixel CCDs," SMPTE J., vol. 111, no. 4, pp. 148-153, Apr. 2002.
2. C. Smith, M. Farrier, K. Mitani, Q. Tang, and G. Ingram, "An 8 M-CCD for an ultra high definition TV cameras," in Proc. IEEE Workshop CCDs, AIS, Nagano, Japan, Jun. 1999, pp. 175-178.
3. I. Takayanagi, M. Shirakawa, K. Mitani, M. Sugawara, S. Iversen, J. Moholt, J. Nakamura, and E. R. Fossum, "A 1-1/4 inch 8.3 M-pixel digital output CMOS APS for UDTV application," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 216-217.
4. I. Takayanagi, M. Shirakawa, K. Mitani, M. Sugawara, S. Iversen, J. Moholt, J. Nakamura, and E. R. Fossum, "A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2305-2314, Nov. 2005.
5. H. Shimamoto, T. Yamashita, N. Koga, K.Mitani, M. Sugawara, F. Okano, M. Matsuoka, J. Shimura, I. Yamamoto, T. Tsukamoto, and S. Yahagi, "An 8 k × 4 k ultrahigh-definition color video camera with 8 M-pixel CMOS imager," SMPTE Motion Imag. J., vol. 114, no. 7/8, pp. 260-268, Jul./Aug. 2005.
6. R. M. Guidash, T.-H. Lee, P. P. K. Lee, D. H. Sackett, C. I. Drowley, M. S. Swenson, L. Arbaugh, R. Hollstein, F. Shapiro, and S. Domer, "A 0.6 μm CMOS pinned photodiode color imager technology," in IEDM Tech. Dig., 1997, pp. 927-929.
7. - noise 1.3 megapixel CMOS sensor," in Proc. IEEE Workshop CCDs, AIS, 2003, pp. 1-6.
8. W. Yang, O.-B. Kwon, J.-I. Lee, G.-T. Hwang, and S.-J. Lee, "An integrated 800 × 600 CMOS imaging system," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 304-305.
9. Y. Nitta, Y. Muramatsu, K. Amano, T. Toyama, J. Yamamoto, K. Mishina, A. Suzuki, T. Taura, A. Kato, M. Kikuchi, Y. Yasui, H. Nomura, and N. Fukushima, "High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2024-2031.
10. S. Yoshihara, Y. Nitta, M. Kikuchi, K. Koseki, Y. Ito, Y. Inada, S. Kuramochi, H. Wakabayashi, M. Okano, H. Kuriyama, J. Inutsuka, A. Tajima, T. Nakajima, Y. Kudoh, F. Koga, Y. Kasagi, S. Watanabe, and T. Nomoto, "A 1/1.8-inch 6.4 M-pixel 60 frame/s CMOS image sensor with seamless mode change," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2998-3006, Dec. 2006.
11. A. I. Krymski, N. E. Bock, N. Tu, D. V. Blerkom, and E. R. Fossum, "A high-speed, 240-frames/s, 4.1-megapixel CMOS sensor," IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 130-135, Jan. 2003.
12. A. Krymski and K. Tajima, "CMOS image sensor with integrated 4 Gb/s camera link transmitter," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2040-2049, Session 27.7.
13. T. Sugiki, S. Ohsawa, H. Miura, M. Sasaki, N. Nakamura, I. Inoue, M. Hoshino, Y. Tomizawa, and T. Arakawa, "A 60mW10 b CMOS image sensor with column-to-column FPN reduction," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 108-109.
14. M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, "A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005.
15. M. Furuta, Y. Nishikawa, T. Inoue, and S. Kawahito, "A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 766-774, Apr. 2007.
16. S. Kawahito, J.-H. Park, K. Isobe, S. Suhaidi, T. Iida, and T. Mizota, "A CMOS image sensor integrating column-parallel cyclic ADCs with on-chip digital error-correction circuits," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 56-57.
17. M. F. Snoeij, A. J. P. Theuwissen, and J. H. Huijsing, "A low-power column-parallel 12-bit ADC for CMOS imagers," in Proc. IEEE Workshop CCDs, AIS, 2005, pp. 169-172.
18. T. Otaka, Y. Lee, T. Bales, P. Smith, J. Macdowell, S. Smith, and I. Takayanagi, "12-bit column-parallel ADC with accelerated ramp," in Proc. IEEE Workshop CCDs, AIS, 2005, pp. 163-176.
19. M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa, and J. H. Huijsing, "Multiple-ramp column-parallel ADC architectures for CMOS image sensors," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2968-2977, Dec. 2007.
20. D. Cline, "Noise, speed, and power trade-offs in pipelined analog to digital converters," Ph.D. dissertation, UC Berkeley, Berkeley, CA, 1995.
21. B. Fotouhi and D. Hodges, "High-resolution A/D conversion in MOS/LSI," IEEE J. Solid-State Circuits, vol. SSC-14, no. 6, pp. 920-926, Dec. 1979.