A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 394-395

  Chae, Youngcheol ^a   Cheon, Jimin ^a   Lim, Seunghyun ^a   Lee, Dongmyung ^a   Kwon, Minho ^b   Yoo, Kwisung ^b   Jung, Wunki ^b   Lee, Dong Hun ^b   Ham, Seogheon ^b   Han, Gunhee ^a  

^a Yonsei University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SIGNAL; CMOS IMAGE SENSOR; CONSUMER MARKET; DECIMATION FILTER; DELTA-SIGMA; HIGH NOISE LEVELS; HIGH POWER CONSUMPTION; HIGH RESOLUTION; HIGH SPEED IMAGING; HIGH-DENSITY; HIGH-SPEED; LOW NOISE; LOW-POWER CONSUMPTION; LOW-POWER OPERATION; PARALLEL ADCS; PIXEL PITCH; SUCCESSIVE APPROXIMATION REGISTER; SYSTEM INTEGRATION;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; IMAGE SENSORS; PARALLEL ARCHITECTURES; SPEED;

PIXELS;

EID: 77952114328     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433974     Document Type: Conference Paper

References (7)

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