A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Volumn , Issue , 2008, Pages 267-270

  Hsu, An Jung ^a   Tu, Chun Chieh ^a   Huang, Shi Yu ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; INDUSTRIAL ENGINEERING; INSTRUMENT DISPLAYS; OSCILLATORS (ELECTRONIC); RAILROAD TUNNELS; SPEED; SPURIOUS SIGNAL NOISE;

ALL DIGITAL PHASE-LOCKED LOOP; HIGH RESOLUTIONS; INTERNATIONAL SYMPOSIUM; VLSI DESIGNS;

BUILT-IN SELF TEST;

EID: 50649095963     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2008.4542464     Document Type: Conference Paper

References (7)

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