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Volumn 46, Issue 7, 1999, Pages 945-950

The design of an all-digital phase-locked loop with small dco hardware and fast phase lock

Author keywords

All digital phase locked loop; Digital control oscillator; Frequency detector; Phase detector; Phase error; Phase locked loop

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CONTROL SYSTEMS; ELECTRIC NETWORK SYNTHESIS; ERROR ANALYSIS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC);

EID: 0032673755     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.775392     Document Type: Article
Times cited : (47)

References (12)
  • 3
    • 0029290063 scopus 로고    scopus 로고
    • 1.5 V 250 MHz operation CMOS phase-locked with precharge type phase-frequency detector, IEICE Trans. Electron., vol. E78-C, no. 4, pp. 381-388, Apr. 1995.
    • H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, A 1.5 V 250 MHz operation CMOS phase-locked with precharge type phase-frequency detector, IEICE Trans. Electron., vol. E78-C, no. 4, pp. 381-388, Apr. 1995.
    • H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, A
    • Kondoh, H.1
  • 7
  • 10
    • 0028552366 scopus 로고    scopus 로고
    • 2-MB/sec CMOS data separator, in ISCAS'94, vol. 3, pp. 53-56.
    • R. Saban and A. Efendovich, A fully-digital, 2-MB/sec CMOS data separator, in ISCAS'94, vol. 3, pp. 53-56.
    • And A. Efendovich, A Fully-digital
    • Saban, R.1
  • 12
    • 0031642059 scopus 로고    scopus 로고
    • 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock, in Proc. ISCAS'98, vol. 3, pp. 554-557.
    • J.-S. Chiang and K.-Y. Chen, A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock, in Proc. ISCAS'98, vol. 3, pp. 554-557.
    • And K.-Y. Chen, A
    • Chiang, J.-S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.