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Volumn , Issue , 2007, Pages 207-210

An all-digital phase-locked loop with high-resolution for SoC applications

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CORRELATION DETECTORS; DIGITAL CONTROL SYSTEMS; INTELLECTUAL PROPERTY; OPTICAL RESOLVING POWER;

EID: 34748877688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2006.258161     Document Type: Conference Paper
Times cited : (31)

References (7)
  • 1
    • 0029289215 scopus 로고
    • An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
    • Apr
    • J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 412-422
    • Dunning, J.1    Garcia, G.2    Lundberg, J.3    Nuckolls, E.4
  • 2
    • 0032673755 scopus 로고    scopus 로고
    • The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock,
    • 46, pp, Jul
    • J. -S Chiang and K. -Y Chen, "The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock,'' IEEE Trans. Circuits Syst. II, vol. 46, pp. 945-950, Jul. 1999.
    • (1999) IEEE Trans. Circuits Syst , vol.2 , pp. 945-950
    • Chiang, J.-S.1    Chen, K.-Y.2
  • 3
    • 0035300186 scopus 로고    scopus 로고
    • Design and analysis of a portable high-speed clock generator
    • Apr
    • T.-Y. Hsu, C.-C. Wang, and C.-Y. Lee, "Design and analysis of a portable high-speed clock generator," IEEE Trans. Circuits Syst. II, vol. 48, pp. 367-375, Apr. 2001.
    • (2001) IEEE Trans. Circuits Syst. II , vol.48 , pp. 367-375
    • Hsu, T.-Y.1    Wang, C.-C.2    Lee, C.-Y.3
  • 4
    • 0037319653 scopus 로고    scopus 로고
    • An all digital phase-locked loop for high-speed clock generation
    • Feb
    • C.-C. Chung and C.-Y. Lee, "An all digital phase-locked loop for high-speed clock generation," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.2 , pp. 347-351
    • Chung, C.-C.1    Lee, C.-Y.2
  • 5
    • 2442446545 scopus 로고    scopus 로고
    • A digitally controlled PLL for Soc Applications
    • May
    • T. Olsson and p. Nilsson, "A digitally controlled PLL for Soc Applications" IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.5 , pp. 751-760
    • Olsson, T.1    Nilsson2
  • 7
    • 11144332005 scopus 로고    scopus 로고
    • A novel digitally-controlled varactor for portable delay cell design
    • Dec
    • P.-L. Chen, C.-C. Chung and C.-Y. Lee, "A novel digitally-controlled varactor for portable delay cell design," IEICE Tran.Fundamentals, vol. E87-A, pp.3324-3326, Dec. 2004.
    • (2004) IEICE Tran.Fundamentals , vol.E87-A , pp. 3324-3326
    • Chen, P.-L.1    Chung, C.-C.2    Lee, C.-Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.