-
1
-
-
0029289215
-
An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
-
Apr
-
J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.4
, pp. 412-422
-
-
Dunning, J.1
Garcia, G.2
Lundberg, J.3
Nuckolls, E.4
-
2
-
-
2442446545
-
A digitally controlled PLL for SoC applications
-
May
-
T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.5
, pp. 751-760
-
-
Olsson, T.1
Nilsson, P.2
-
3
-
-
0037319653
-
An all digital phase-locked loop for high-speed clock generation
-
Feb
-
C.-C. Chung and C.-Y. Lee, "An all digital phase-locked loop for high-speed clock generation," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.2
, pp. 347-351
-
-
Chung, C.-C.1
Lee, C.-Y.2
-
4
-
-
34748877688
-
An all-digital phase-locked loop with high-resolution for SoC applications
-
Apr
-
D. Sheng, C.-C. Chung, and C.-Y. Lee, "An all-digital phase-locked loop with high-resolution for SoC applications," in Proc. IEEE VLSIDAT Apr. 2006, pp. 207-210.
-
(2006)
Proc. IEEE VLSIDAT
, pp. 207-210
-
-
Sheng, D.1
Chung, C.-C.2
Lee, C.-Y.3
-
5
-
-
33947609587
-
All-digital PLL with ultra fast settling
-
Jan
-
R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, "All-digital PLL with ultra fast settling," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 2, pp. 181-185, Jan. 2007.
-
(2007)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.54
, Issue.2
, pp. 181-185
-
-
Staszewski, R.B.1
Leipold, D.2
Muhammad, K.3
Balsara, P.T.4
-
6
-
-
27844469031
-
A monotonic digitally controlled delay element
-
Nov
-
M. Maymandi-Nejad and M. Sachdev, "A monotonic digitally controlled delay element," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2212-2219, Nov. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.11
, pp. 2212-2219
-
-
Maymandi-Nejad, M.1
Sachdev, M.2
-
7
-
-
0344512371
-
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process
-
Nov
-
R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 815-828, Nov. 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.50
, Issue.11
, pp. 815-828
-
-
Staszewski, R.B.1
Leipold, D.2
Muhammad, K.3
Balsara, P.T.4
-
8
-
-
0037968905
-
A delay-line based DCO for multimedia applications using digital standard cells only
-
Feb
-
E. Roth, M. Thalmann, N. Felber, and W. Fichtner, "A delay-line based DCO for multimedia applications using digital standard cells only," in Proc. Dig. Tech. Papers ISSCC'03, Feb. 2003, pp. 432-433.
-
(2003)
Proc. Dig. Tech. Papers ISSCC'03
, pp. 432-433
-
-
Roth, E.1
Thalmann, M.2
Felber, N.3
Fichtner, W.4
-
9
-
-
20444385790
-
A portable digitally controlled oscillator using novel varactors
-
May
-
P.-L. Chen, C.-C. Chung, and C.-Y. Lee, "A portable digitally controlled oscillator using novel varactors," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 5, pp. 233-237, May 2005.
-
(2005)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.52
, Issue.5
, pp. 233-237
-
-
Chen, P.-L.1
Chung, C.-C.2
Lee, C.-Y.3
|