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Volumn , Issue , 2007, Pages 246-249

The coming of age of physical synthesis

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER-AIDED DESIGN; DESIGN TRENDS; EDA INDUSTRY; INTERNATIONAL CONFERENCES; LOGIC SYNTHESIS; PHYSICAL DESIGNS; PHYSICAL SYNTHESIS;

EID: 43349086145     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397273     Document Type: Conference Paper
Times cited : (29)

References (16)
  • 4
    • 0033697586 scopus 로고    scopus 로고
    • Can recursive bisection produce routable placements
    • A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection produce routable placements. In Proc. ACM/IEEE DAC. pages 477-482, 2000.
    • (2000) Proc. ACM/IEEE DAC , pp. 477-482
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 5
    • 0031632293 scopus 로고    scopus 로고
    • Generic global placement and floorplanning
    • H. Eisenmann and F. Johannes. Generic global placement and floorplanning. In Proc. ACM/IEEE DAC, pages 269-274, 1998.
    • (1998) Proc. ACM/IEEE DAC , pp. 269-274
    • Eisenmann, H.1    Johannes, F.2
  • 7
    • 33745944475 scopus 로고    scopus 로고
    • ISPD 2006 placement contest: Benchmark suite and results
    • G.-J. Nam. ISPD 2006 placement contest: Benchmark suite and results. In Proc. ISPD, page 167, 2006.
    • (2006) Proc. ISPD , pp. 167
    • Nam, G.-J.1
  • 8
    • 2942639682 scopus 로고    scopus 로고
    • FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
    • Natarajan Viswanathan and Chris Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. ISPD, pages 26-33, 2004.
    • (2004) Proc. ISPD , pp. 26-33
    • Viswanathan, N.1    Chu, C.2
  • 10
    • 2942672235 scopus 로고    scopus 로고
    • Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat
    • Pete Osier. Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. In Proc. ISPD. pages 190-197, 2004.
    • (2004) Proc. ISPD , pp. 190-197
    • Osier, P.1
  • 11
    • 46649104482 scopus 로고    scopus 로고
    • FastRoute 2.0: A high-quality and efficient global router
    • Min Pan and Chris Chu. FastRoute 2.0: A high-quality and efficient global router. In Proc. ASPDAC, pages 250-255, 2007.
    • (2007) Proc. ASPDAC , pp. 250-255
    • Pan, M.1    Chu, C.2
  • 12
    • 50249112785 scopus 로고    scopus 로고
    • FLUTE: Fast lookup table base rectilinear Steiner minimal tree algorithm for VLSI design
    • Chris Chu and Yiu-Chung Wong. FLUTE: Fast lookup table base rectilinear Steiner minimal tree algorithm for VLSI design. IEEE TCAD, 2007.
    • (2007) IEEE TCAD
    • Chu, C.1    Wong, Y.-C.2
  • 13
    • 34547267305 scopus 로고    scopus 로고
    • IPR: An integrated placement and routing algorithm
    • Min Pan and Chris Chu. IPR: An integrated placement and routing algorithm. In Proc. ACM/IEEE DAC, pages 59-62, 2007.
    • (2007) Proc. ACM/IEEE DAC , pp. 59-62
    • Pan, M.1    Chu, C.2
  • 14
    • 0027832525 scopus 로고
    • Optimal wiresizing under the distributed Elmore delay model
    • Jason Cong and Kwok-Shing Leung. Optimal wiresizing under the distributed Elmore delay model. In Proc. IEEE/ACM ICCAD. pages 634-639, 1993.
    • (1993) Proc. IEEE/ACM ICCAD , pp. 634-639
    • Cong, J.1    Leung, K.-S.2
  • 16
    • 0035065457 scopus 로고    scopus 로고
    • Interconnect synthesis without wire tapering
    • January
    • Charles J. Alpert. Anirudh Devgan, John Fishburn, and Stephen T. Quay. Interconnect synthesis without wire tapering. IEEE TCAD, 20(1):90-104, January 2000.
    • (2000) IEEE TCAD , vol.20 , Issue.1 , pp. 90-104
    • Alpert, C.J.1    Devgan, A.2    Fishburn, J.3    Quay, S.T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.