-
1
-
-
43349096114
-
Techniques for fast physical synthesis
-
March
-
C.J. Alpert, S. K. Karandikar, Z. Li. G.-J. Nam, S. T. Quay. H. Ren, C. N. Sze, P. G. Villarrubia, and M. C. Yildiz. Techniques for fast physical synthesis. Proc. of IEEE, 95(3):573-599, March 2007.
-
(2007)
Proc. of IEEE
, vol.95
, Issue.3
, pp. 573-599
-
-
Alpert, C.J.1
Karandikar, S.K.2
Nam, Z.L.G.-J.3
Quay, S.T.4
Ren, H.5
Sze, C.N.6
Villarrubia, P.G.7
Yildiz, M.C.8
-
3
-
-
1342323840
-
An integrated environment for technology closure of deep-submicron IC designs
-
14-22, JanFeb
-
L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, and M. A. Kazda. An integrated environment for technology closure of deep-submicron IC designs. IEEE Design and Test of Computers. 21(1): 14-22, JanFeb 2004.
-
(2004)
IEEE Design and Test of Computers
, vol.21
, Issue.1
-
-
Trevillyan, L.1
Kung, D.2
Puri, R.3
Reddy, L.N.4
Kazda, M.A.5
-
5
-
-
0031632293
-
Generic global placement and floorplanning
-
H. Eisenmann and F. Johannes. Generic global placement and floorplanning. In Proc. ACM/IEEE DAC, pages 269-274, 1998.
-
(1998)
Proc. ACM/IEEE DAC
, pp. 269-274
-
-
Eisenmann, H.1
Johannes, F.2
-
6
-
-
29144447716
-
The ISPD2005 placement contest and benchmark suite
-
G.-J. Nam, C. J. Alpert, P. Villarubbia, B. Winter, and M. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proc. ISPD, pages 216-220, 2005.
-
(2005)
Proc. ISPD
, pp. 216-220
-
-
Nam, G.-J.1
Alpert, C.J.2
Villarubbia, P.3
Winter, B.4
Yildiz, M.5
-
7
-
-
33745944475
-
ISPD 2006 placement contest: Benchmark suite and results
-
G.-J. Nam. ISPD 2006 placement contest: Benchmark suite and results. In Proc. ISPD, page 167, 2006.
-
(2006)
Proc. ISPD
, pp. 167
-
-
Nam, G.-J.1
-
8
-
-
2942639682
-
FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
-
Natarajan Viswanathan and Chris Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. ISPD, pages 26-33, 2004.
-
(2004)
Proc. ISPD
, pp. 26-33
-
-
Viswanathan, N.1
Chu, C.2
-
10
-
-
2942672235
-
Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat
-
Pete Osier. Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. In Proc. ISPD. pages 190-197, 2004.
-
(2004)
Proc. ISPD
, pp. 190-197
-
-
Osier, P.1
-
11
-
-
46649104482
-
FastRoute 2.0: A high-quality and efficient global router
-
Min Pan and Chris Chu. FastRoute 2.0: A high-quality and efficient global router. In Proc. ASPDAC, pages 250-255, 2007.
-
(2007)
Proc. ASPDAC
, pp. 250-255
-
-
Pan, M.1
Chu, C.2
-
12
-
-
50249112785
-
FLUTE: Fast lookup table base rectilinear Steiner minimal tree algorithm for VLSI design
-
Chris Chu and Yiu-Chung Wong. FLUTE: Fast lookup table base rectilinear Steiner minimal tree algorithm for VLSI design. IEEE TCAD, 2007.
-
(2007)
IEEE TCAD
-
-
Chu, C.1
Wong, Y.-C.2
-
13
-
-
34547267305
-
IPR: An integrated placement and routing algorithm
-
Min Pan and Chris Chu. IPR: An integrated placement and routing algorithm. In Proc. ACM/IEEE DAC, pages 59-62, 2007.
-
(2007)
Proc. ACM/IEEE DAC
, pp. 59-62
-
-
Pan, M.1
Chu, C.2
-
14
-
-
0027832525
-
Optimal wiresizing under the distributed Elmore delay model
-
Jason Cong and Kwok-Shing Leung. Optimal wiresizing under the distributed Elmore delay model. In Proc. IEEE/ACM ICCAD. pages 634-639, 1993.
-
(1993)
Proc. IEEE/ACM ICCAD
, pp. 634-639
-
-
Cong, J.1
Leung, K.-S.2
-
16
-
-
0035065457
-
Interconnect synthesis without wire tapering
-
January
-
Charles J. Alpert. Anirudh Devgan, John Fishburn, and Stephen T. Quay. Interconnect synthesis without wire tapering. IEEE TCAD, 20(1):90-104, January 2000.
-
(2000)
IEEE TCAD
, vol.20
, Issue.1
, pp. 90-104
-
-
Alpert, C.J.1
Devgan, A.2
Fishburn, J.3
Quay, S.T.4
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