DeltaSyn: An efficient logic difference optimizer for ECO synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 789-796

  Krishnaswamy, Smita ^a   Ren, Haoxing ^a   Modi, Nilesh ^b   Puri, Ruchir ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-PARALLEL; DESIGN CYCLE; DESIGN PROCESS; DYNAMIC ALGORITHM; FUNCTIONAL SPECIFICATION; HIGH LEVEL SPECIFICATION; IC DESIGNS; INDUSTRIAL DESIGN; OPTIMIZERS; PLACEMENT AND ROUTING; SAT SOLVERS; SECOND PHASE; TWO PHASIS;

SPECIFICATIONS; STRUCTURAL ANALYSIS;

COMPUTER AIDED DESIGN;

EID: 76349086662     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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