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Volumn 2000-January, Issue , 2000, Pages 236-243

Incremental CAD

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DESIGN; LOGIC DESIGN; LOGIC SYNTHESIS; SYNTHESIS (CHEMICAL); ERROR CORRECTION; ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS; ITERATIVE METHODS;

EID: 0034474816     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896480     Document Type: Conference Paper
Times cited : (32)

References (57)
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    • J. Cong, C.-K. Koh, and P. Madden. Performance optimization of VLSI interconnect layout. Intergration, the VLSI Journal, 21(1-2):1-94, .
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    • Interconnect layout optimization by simultaneous steiner tree construction and buffer insertion
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.