메뉴 건너뛰기




Volumn , Issue , 2010, Pages 227-236

Characterization and exploitation of narrow-width loads: The narrow-width cache approach

Author keywords

Narrow width cache; Narrow width load; Small value locality

Indexed keywords

AREA OVERHEAD; BENCHMARK SUITES; INPUT DATAS; NARROW WIDTH; VALUE LOCALITY;

EID: 78650653796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1878921.1878955     Document Type: Conference Paper
Times cited : (10)

References (25)
  • 1
    • 4644245377 scopus 로고    scopus 로고
    • Adaptive cache compression for high-performance processors
    • A. R. Alameldeen and D. A. Wood, "Adaptive Cache Compression for High-Performance Processors, " In Proc. ISCA-31, pp. 212-223, 2004.
    • (2004) Proc. ISCA-31 , pp. 212-223
    • Alameldeen, A.R.1    Wood, D.A.2
  • 2
    • 0032778066 scopus 로고    scopus 로고
    • Dynamically exploiting narrow width operands to improve processor power and performance
    • D. Brooks, and M. Martonosi, "Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance, " In Proc. HPCA-5, pp. 13, 1999.
    • (1999) Proc. HPCA-5 , pp. 13
    • Brooks, D.1    Martonosi, M.2
  • 3
    • 0002525825 scopus 로고    scopus 로고
    • Value-based clock gating and operation packing: Dynamic strategies for improving processor power and performance
    • May
    • D. Brooks, and M. Martonosi, "Value-based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance", ACM Trans. Comput. Syst. 18, 2 (May. 2000), 89-126.
    • (2000) ACM Trans. Comput. Syst. , vol.18 , Issue.2 , pp. 89-126
    • Brooks, D.1    Martonosi, M.2
  • 4
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, " In Proc. ISCA-27, pp. 83-94, 2000.
    • (2000) Proc. ISCA-27 , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 6
    • 0034460898 scopus 로고    scopus 로고
    • Very low power pipelines using significance compression
    • R. Canal, A. González, and J. E. Smith, "Very Low Power Pipelines using Significance Compression", In Proc. MICRO-33, pp. 181-190, 2000.
    • (2000) Proc. MICRO-33 , pp. 181-190
    • Canal, R.1    González, A.2    Smith, J.E.3
  • 7
    • 27544435752 scopus 로고    scopus 로고
    • A robust main-memory compression scheme
    • M. Ekman and P. Stenstrom, "A Robust Main-Memory Compression Scheme, " In Proc. ISCA-32, pp. 74-85, 2005.
    • (2005) Proc. ISCA-32 , pp. 74-85
    • Ekman, M.1    Stenstrom, P.2
  • 8
    • 21644435605 scopus 로고    scopus 로고
    • Register packing: Exploiting narrow-width operands for reducing register file pressure
    • O. Ergin, D. Balkan, K. Ghose, and D. Ponomarev, "Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, " In Proc. MICRO-37, pp. 304-315, 2004.
    • (2004) Proc. MICRO-37 , pp. 304-315
    • Ergin, O.1    Balkan, D.2    Ghose, K.3    Ponomarev, D.4
  • 10
    • 70449643567 scopus 로고    scopus 로고
    • Zero-value caches: Cancelling loads that return zero
    • M. M. Islam and P. Stenstrom, "Zero-Value Caches: Cancelling Loads that Return Zero, " In Proc. PACT 2009, pp. 237-245, 2009.
    • (2009) Proc. PACT 2009 , pp. 237-245
    • Islam, M.M.1    Stenstrom, P.2
  • 12
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded SPARC processor
    • P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded SPARC Processor, " IEEE Micro: 21- 29, 2005.
    • (2005) IEEE Micro , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 14
    • 69249220832 scopus 로고    scopus 로고
    • Exploiting data-width locality to increase superscalar execution bandwidth
    • G. H. Loh, "Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth, " In Proc. MICRO-35, pp. 395-405, 2002.
    • (2002) Proc. MICRO-35 , pp. 395-405
    • Loh, G.H.1
  • 16
    • 84933069131 scopus 로고    scopus 로고
    • Just say no: Benefits of early cache miss determination
    • G. Memik, G. Reinman, and W. H. Mangione-Smith, "Just Say No: Benefits of Early Cache Miss Determination, " In Proc. HPCA-9, pp. 307-316, 2003.
    • (2003) Proc. HPCA-9 , pp. 307-316
    • Memik, G.1    Reinman, G.2    Mangione-Smith, W.H.3
  • 17
    • 33748547225 scopus 로고    scopus 로고
    • Restrictive compression techniques to increase level 1 cache capacity
    • P. Pujara, and A. Aggarwal, "Restrictive Compression Techniques to Increase Level 1 Cache Capacity, " In Proc. ICCD, pp. 327-333, 2005.
    • (2005) Proc. ICCD , pp. 327-333
    • Pujara, P.1    Aggarwal, A.2
  • 18
    • 46649121102 scopus 로고    scopus 로고
    • A case for a complexity-effective, width-partitioned microarchitecture
    • Sep.
    • O. Rochecouste, G. Pokam, and A. Seznec, "A Case for a Complexity-Effective, Width-Partitioned Microarchitecture, " ACM Trans. Archit. Code Optim. 3, 3 (Sep. 2006), 295-326.
    • (2006) ACM Trans. Archit. Code Optim , vol.3 , Issue.3 , pp. 295-326
    • Rochecouste, O.1    Pokam, G.2    Seznec, A.3
  • 19
    • 0036953769 scopus 로고    scopus 로고
    • Automatically characterizing large scale program behavior
    • T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program Behavior, " In Proc. ASPLOS, pp. 45-57, 2002.
    • (2002) Proc. ASPLOS , pp. 45-57
    • Sherwood, T.1    Perelman, E.2    Hamerly, G.3    Calder, B.4
  • 21
    • 55849097247 scopus 로고    scopus 로고
    • Memory-link compression schemes: A value locality perspective
    • July
    • M. Thuresson, L. Spracklen, and P. Stenstrom, "Memory- Link Compression Schemes: A Value Locality Perspective, " IEEE Transactions on Computers, v.57 n.7, p.916-927, July 2008.
    • (2008) IEEE Transactions on Computers , vol.57 , Issue.7 , pp. 916-927
    • Thuresson, M.1    Spracklen, L.2    Stenstrom, P.3
  • 22
    • 0034461412 scopus 로고    scopus 로고
    • Dynamic zero compression for cache energy reduction
    • L. Villa, M. Zhang, and K. Asanovic, "Dynamic Zero Compression for Cache Energy Reduction, " In Proc. MICRO-33, pp. 214-220, 2000.
    • (2000) Proc. MICRO-33 , pp. 214-220
    • Villa, L.1    Zhang, M.2    Asanovic, K.3
  • 24
    • 84948961559 scopus 로고    scopus 로고
    • Energy efficient frequent value data cache design
    • J. Yang and R. Gupta, "Energy Efficient Frequent Value Data Cache Design, " In Proc. MICRO-35, pp. 197-207, 2002.
    • (2002) Proc. MICRO-35 , pp. 197-207
    • Yang, J.1    Gupta, R.2
  • 25
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS r10000 superscalar microprocessor
    • K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor, " IEEE Micro, 16(2): 28-40, 1996.
    • (1996) IEEE Micro , vol.16 , Issue.2 , pp. 28-40
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.