-
1
-
-
0029322021
-
MOS transistors: Scaling and performance trends
-
Jun.
-
M. Bohr, "MOS transistors: Scaling and performance trends," Semicond. Int., vol. 18, no. 6, pp. 75-79, Jun. 1995
-
(1995)
Semicond. Int.
, vol.18
, Issue.6
, pp. 75-79
-
-
Bohr, M.1
-
3
-
-
0029535575
-
Quantitative understanding of inversion-layer capacitance in Si MOSFETs
-
Dec.
-
S. Takagi and A. Toriumi, "Quantitative understanding of inversion-layer capacitance in Si MOSFETs," IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2125-2130, Dec. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.12
, pp. 2125-2130
-
-
Takagi, S.1
Toriumi, A.2
-
5
-
-
36549091403
-
Quantum capacitance devices
-
Feb.
-
S. Luryi, "Quantum capacitance devices," Appl. Phys. Lett., vol. 52, no. 6, pp. 501-503, Feb. 1988.
-
(1988)
Appl. Phys. Lett.
, vol.52
, Issue.6
, pp. 501-503
-
-
Luryi, S.1
-
6
-
-
0031117193
-
Scaled silicon MOSFETs: Degradation of the total gate capacitance
-
Apr.
-
D. Vasileska, D. K. Schroder, and D. K. Ferry, "Scaled silicon MOSFETs: Degradation of the total gate capacitance," IEEE Trans. Electron Devices, vol. 44, no. 4, pp. 584-587, Apr. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.4
, pp. 584-587
-
-
Vasileska, D.1
Schroder, D.K.2
Ferry, D.K.3
-
7
-
-
0032630404
-
The influence of space quantization effects on the threshold voltage, inversion layer and total gate capacitances in scaled Si-MOSFETs
-
Jun.
-
D. Vasileska and D. K. Ferry, "The influence of space quantization effects on the threshold voltage, inversion layer and total gate capacitances in scaled Si-MOSFETs," Nanotechnology, vol. 10, no. 2, pp. 192-197, Jun. 1999.
-
(1999)
Nanotechnology
, vol.10
, Issue.2
, pp. 192-197
-
-
Vasileska, D.1
Ferry, D.K.2
-
8
-
-
40949165797
-
Influence of bandstructure and channel structure on the inversion layer capacitance of silicon and GaAs MOSFETs
-
Mar.
-
H. S. Pal, K. D. Cantley, S. S. Ahmed, and M. S. Lundstrom, "Influence of bandstructure and channel structure on the inversion layer capacitance of silicon and GaAs MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 904-908, Mar. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.3
, pp. 904-908
-
-
Pal, H.S.1
Cantley, K.D.2
Ahmed, S.S.3
Lundstrom, M.S.4
-
9
-
-
0038104277
-
High performance fully-depleted tri-gate CMOS transistors
-
Apr.
-
B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.4
, pp. 263-265
-
-
Doyle, B.S.1
Datta, S.2
Doczy, M.3
Hareland, S.4
Jin, B.5
Kavalieros, J.6
Linton, T.7
Murthy, A.8
Rios, R.9
Chau, R.10
-
10
-
-
0038020059
-
Influence of channel width on n-and p-type nano-wire-MOSFETs on silicon on insulator substrate
-
Jun.
-
M. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Heuser, M. Baus, O. Winkler, B. Spangenberg, R. Granzner, F. Schwierz, and H. Kurz, "Influence of channel width on n-and p-type nano-wire-MOSFETs on silicon on insulator substrate," Microelectron. Eng., vol. 67/68, pp. 810-817, Jun. 2003.
-
(2003)
Microelectron. Eng.
, vol.67-68
, pp. 810-817
-
-
Lemme, M.1
Mollenhauer, T.2
Henschel, W.3
Wahlbrink, T.4
Heuser, M.5
Baus, M.6
Winkler, O.7
Spangenberg, B.8
Granzner, R.9
Schwierz, F.10
Kurz, H.11
-
11
-
-
0842309837
-
2 6T-SRAM cell with 45 nm gate length triple gate transistors
-
2 6T-SRAM cell with 45 nm gate length triple gate transistors," in IEDM Tech. Dig., 2003, pp. 23-26.
-
(2003)
IEDM Tech. Dig.
, pp. 23-26
-
-
Yang, J.-H.1
Jin, Y.-S.2
Lee, H.-R.3
Rha, K.-S.4
Choi, J.-A.5
Bae, S.-K.6
Maeda, S.7
Kim, Y.-W.8
Suh, K.-P.9
-
12
-
-
33646271349
-
High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices
-
May
-
N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices, IEEE Electron Device Lett. 27,no 5.,pp 383-386, May. 2006
-
(2006)
IEEE Electron Device Lett.
, vol.27
, Issue.5
, pp. 383-386
-
-
Singh, N.1
Agarwal, A.2
Bera, L.K.3
Liow, T.Y.4
Yang, R.5
Rustagi, S.C.6
Tung, C.H.7
Kumar, R.8
Lo, G.Q.9
Balasubramanian, N.10
Kwong, D.-L.11
-
13
-
-
46049102044
-
Gate-All-Around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires
-
K. H. Yeo, S. D. Suk, M. Li, Y. Yeoh, K. H. Cho, K.-H. Hong, S. K. Yun, M. S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "Gate-All-Around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires," in IEDM Tech. Dig., 2006, pp. 539-542.
-
(2006)
IEDM Tech. Dig.
, pp. 539-542
-
-
Yeo, K.H.1
Suk, S.D.2
Li, M.3
Yeoh, Y.4
Cho, K.H.5
Hong, K.-H.6
Yun, S.K.7
Lee, M.S.8
Cho, N.9
Lee, K.10
Hwang, D.11
Park, B.12
Kim, D.-W.13
Park, D.14
Ryu, B.-I.15
-
14
-
-
9744264882
-
Quantum capacitance in nanoscale device modeling
-
Nov.
-
D. L. John, L. C. Castro, and D. L. Pulfrey, "Quantum capacitance in nanoscale device modeling,"J. Appl. Phys., vol. 96, no. 9, pp. 5180-5184, Nov. 2004.
-
(2004)
J. Appl. Phys.
, vol.96
, Issue.9
, pp. 5180-5184
-
-
John, D.L.1
Castro, L.C.2
Pulfrey, D.L.3
-
15
-
-
0041761616
-
Theory of ballistic nanotransistors
-
Sep.
-
A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, "Theory of ballistic nanotransistors," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1853-1864, Sep. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.9
, pp. 1853-1864
-
-
Rahman, A.1
Guo, J.2
Datta, S.3
Lundstrom, M.S.4
-
16
-
-
41749110900
-
Outperforming the conventional scaling rules in the quantum-capacitance limit
-
Apr.
-
J. Knoch, W. Riess, and J. Appenzeller, "Outperforming the conventional scaling rules in the quantum-capacitance limit," IEEE Electron Device Lett., vol. 29, no. 4, pp. 372-374, Apr. 2008.
-
(2008)
IEEE Electron Device Lett.
, vol.29
, Issue.4
, pp. 372-374
-
-
Knoch, J.1
Riess, W.2
Appenzeller, J.3
-
17
-
-
56549083690
-
Scaling of nanowire transistors
-
Nov.
-
B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Taur, "Scaling of nanowire transistors," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2846-2858, Nov. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.11
, pp. 2846-2858
-
-
Yu, B.1
Wang, L.2
Yuan, Y.3
Asbeck, P.M.4
Taur, Y.5
-
18
-
-
33751237995
-
A numerical Schrödinger-Poisson solver for radially symmetric nanowire core-shell structures
-
Nov./Dec.
-
L. Wang, D. Wang, and P. M. Asbeck, "A numerical Schrödinger-Poisson solver for radially symmetric nanowire core-shell structures," Solid State Electron., vol. 50, no. 11/12, pp. 1732-1739, Nov./Dec. 2006.
-
(2006)
Solid State Electron.
, vol.50
, Issue.11-12
, pp. 1732-1739
-
-
Wang, L.1
Wang, D.2
Asbeck, P.M.3
-
19
-
-
21644484375
-
3D quantum modelling and simulation of multiple-gate nanowire MOSFETs
-
M. Bescond, K. Nehari, J. L. Autran, N. Cavassilas, D. Munteanu, and M. Lannoo, "3D quantum modelling and simulation of multiple-gate nanowire MOSFETs," in IEDM Tech. Dig., 2004, pp. 617-620.
-
(2004)
IEDM Tech. Dig.
, pp. 617-620
-
-
Bescond, M.1
Nehari, K.2
Autran, J.L.3
Cavassilas, N.4
Munteanu, D.5
Lannoo, M.6
-
20
-
-
38149018536
-
A comprehensive study of the corner effects in pi-gate SOI MOSFETs including quantum effects
-
Dec.
-
F. J. G. Ruiz, A. Godoy, F. Gámiz, C. Sampedro, and L. Donetti, "A comprehensive study of the corner effects in pi-gate SOI MOSFETs including quantum effects," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3369-3377, Dec. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.12
, pp. 3369-3377
-
-
Ruiz, F.J.G.1
Godoy, A.2
Gámiz, F.3
Sampedro, C.4
Donetti, L.5
-
21
-
-
70350707600
-
Equivalent oxide thickness of trigate SOI MOSFETs with high-κ insulators
-
Nov.
-
F. J. G. Ruiz, I. M. Tienda-Luna, A. Godoy, L. Donetti, and F. Gámiz, "Equivalent oxide thickness of trigate SOI MOSFETs with high-κ insulators," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2711-2719, Nov. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.11
, pp. 2711-2719
-
-
Ruiz, F.J.G.1
Tienda-Luna, I.M.2
Godoy, A.3
Donetti, L.4
Gámiz, F.5
-
22
-
-
78650023434
-
-
NEXTNANO\Next Generation 3D Nanodevice Simulator. [Online]. Available:
-
NEXTNANO\Next Generation 3D Nanodevice Simulator. [Online]. Available: www.nextnano.de/nextnano3
-
-
-
-
23
-
-
41349092986
-
NEXTNANO: General purpose 3-D simulations
-
Sep.
-
S. Birner, T. Zibold, T. Andlauer, T. Kubis, M. Sabathil, A. Trellakis, and P. Vogl, "NEXTNANO: General purpose 3-D simulations," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2137-2142, Sep. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.9
, pp. 2137-2142
-
-
Birner, S.1
Zibold, T.2
Andlauer, T.3
Kubis, T.4
Sabathil, M.5
Trellakis, A.6
Vogl, P.7
-
24
-
-
0036564041
-
Quantum C-V modeling in depletion and inversion: Accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs
-
May
-
W Quan, D. M. Kim, and H.-D. Lee, "Quantum C-V modeling in depletion and inversion: Accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 889-894, May 2002
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.5
, pp. 889-894
-
-
Quan, W.1
Kim, D.M.2
Lee, H.-D.3
|