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Volumn , Issue , 2010, Pages 341-344

SOI TFETs: Suppression of ambipolar leakage and low-frequency noise behavior

Author keywords

[No Author keywords available]

Indexed keywords

AMBIPOLAR; EFFECTIVE GATE LENGTH; LOW-FREQUENCY NOISE; MOSFETS; SOI SUBSTRATES; SOURCE-DRAIN LEAKAGE; TEMPERATURE DEPENDENCE; THIN BODY; TUNNELING FIELD-EFFECT TRANSISTORS;

EID: 78649964022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2010.5618222     Document Type: Conference Paper
Times cited : (33)

References (15)
  • 1
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    • Reddick, W.M.1    Amaratunga, G.A.J.2
  • 2
    • 64849115310 scopus 로고    scopus 로고
    • Can the interband tunnel FET outperform Si CMOS?
    • Q. Zhang and A. Seabaugh, "Can the interband tunnel FET outperform Si CMOS?, " DRC, PP. 73-74, 2008.
    • (2008) DRC , pp. 73-74
    • Zhang, Q.1    Seabaugh, A.2
  • 3
    • 70350705816 scopus 로고    scopus 로고
    • Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits
    • Y. Khatami and K. Banerjee, "Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits, " IEEE Trans. Electron Devices, vol. 56, pp. 2752-2761, 2009.
    • (2009) IEEE Trans. Electron Devices , vol.56 , pp. 2752-2761
    • Khatami, Y.1    Banerjee, K.2
  • 7
    • 64549108830 scopus 로고    scopus 로고
    • Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec subthreshold slope
    • T. Krishnamohan, D. Kim, S. Raghunathan and K. Saraswat, "Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec subthreshold slope, " IEDM Tech. Dig., pp. 947-949, 2008.
    • (2008) IEDM Tech. Dig. , pp. 947-949
    • Krishnamohan, T.1    Kim, D.2    Raghunathan, S.3    Saraswat, K.4
  • 8
    • 23944478215 scopus 로고    scopus 로고
    • A simulation approach to optimize the electrical parameters of a vertical tunnel FET
    • K. K Bhuwalka, J. Schulze and I. Eisele, "A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET, " IEEE Trans. Electron Devices, vol. 52, pp. 1541-1547, 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , pp. 1541-1547
    • Bhuwalka, K.K.1    Schulze, J.2    Eisele, I.3
  • 10
    • 0036540242 scopus 로고    scopus 로고
    • Electrical noise and RTS fluctuations in advanced CMOS devices
    • G. Ghibaudo and T. Boutchacha, "Electrical noise and RTS fluctuations in advanced CMOS devices, " Microelectron Reliab, vol. 42, pp. 573- 582, 2002.
    • (2002) Microelectron Reliab , vol.42 , pp. 573-582
    • Ghibaudo, G.1    Boutchacha, T.2
  • 12
    • 34547850370 scopus 로고    scopus 로고
    • Tunneling fieldeffect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec
    • W. Y. Choi, B. G. Park, J. D. Lee, and T. K. Liu, "Tunneling fieldeffect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, " IEEE Electron Device Lett., vol. 28, pp. 743-745, 2007.
    • (2007) IEEE Electron Device Lett. , vol.28 , pp. 743-745
    • Choi, W.Y.1    Park, B.G.2    Lee, J.D.3    Liu, T.K.4
  • 13
    • 41949092207 scopus 로고    scopus 로고
    • The tunnel source (PNPN) n-MOSFET: A novel high performance transistor
    • V. Nagavarapu, R. Jhaveri, and J. C. S. Woo, "The tunnel source (PNPN) n-MOSFET: a novel high performance transistor, " IEEE Trans. Electron Dev., vol. 55, pp. 1013-1019, 2008.
    • (2008) IEEE Trans. Electron Dev. , vol.55 , pp. 1013-1019
    • Nagavarapu, V.1    Jhaveri, R.2    Woo, J.C.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.