Gate semi-around Si nanowire FET fabricated by conventional CMOS process with very high drivability

2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Volumn , Issue , 2010, Pages 361-364

  Sato, Soshi ^a   Lee, Yeonghun ^a   Kakushima, Kuniyuki ^a   Ahmet, Parhat ^a   Ohmori, Kenji ^b   Natori, Kenji ^a   Yamada, Keisaku ^b   Iwai, Hiroshi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER DENSITY; CMOS PROCESSS; ELECTRICAL CHARACTERISTIC; GATE LENGTH; HIGH PERFORMANCE DEVICES; ON-CURRENTS; OXIDE THICKNESS; SERIES RESISTANCES; SI NANOWIRE; SILICON NANOWIRES; WIRE SIZE;

CMOS INTEGRATED CIRCUITS; ELECTRIC WIRE; MESFET DEVICES; NANOWIRES; SOLID STATE DEVICES;

CARRIER MOBILITY;

EID: 78649914531     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2010.5618212     Document Type: Conference Paper

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