High-performance Si nanowire FET with a semi gate-around structure suitable for integration

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Volumn , Issue , 2009, Pages 249-252

  Sato, Soshi ^a   Kamimura, Hideyuki ^a   Arai, Hideaki ^a   Kakushima, Kuniyuki ^a   Ahmet, Parhat ^a   Ohmori, Kenji ^b   Yamada, Keisaku ^b   Iwai, Hiroshi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; ETCHING STEP; GATE LENGTH; GATE OXIDE THICKNESS; HIGH MOBILITY; NANOWIRE FET; OFF-CURRENT; ON-CURRENTS; SI NANOWIRE; SILICON NANOWIRES; STRUCTURE-BASED;

MESFET DEVICES; NANOWIRES; SILICON; SILICON NITRIDE; SILICON OXIDES;

FIELD EFFECT TRANSISTORS;

EID: 72849143036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2009.5331825     Document Type: Conference Paper

References (8)

1. H. Iwai, IEDM 2008 short cource
2. R. Wang, H. Liu, R. Huang, J. Zhuge, L. Zahng, D. W. Kim, X. Zhang, D. Park, and Y. Wang, "Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility", IEDM 2008.
3. Y. Jiang, T. Y. Liow, N. Singh, L. H. Tan, G. Q. Lo, D.S. H. Chan and D. L. Kwong, "Performance Breakthrough in 8nm Gate Length Gate-All-Around Nanowire Transistors using Metallic Nanowire Contacts", VLSI Tech. Symp. 2008.
4. T tuneability, IEDM 2008.
5. C. Jiezhi, T. Saraya, K. Miyaji, K. Shimizu. T.Hiramoto, "Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI", Symp. On VLSI. Tech, 2008.
6. T. Sato, Y. Takeishi, H. Hara, "Mobility Anisotropy of Electrons in Inversion Layers on Oxidized Silicon Surfaces, Physical Review B, 4, 1950,19.
7. National Technology Roadmap for Semiconductors, Semiconductor Industry Assosiation, 1997.
8. International Technology Roadmap for Semiconductor Roadmap, 2007.