-
1
-
-
0032116366
-
Future system-on-silicon LSI chips
-
Jul./Aug.
-
M. Koyanagi, H. Kurino, K.-W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp. 17-22, Jul./Aug. 1998.
-
(1998)
IEEE Micro
, vol.18
, Issue.4
, pp. 17-22
-
-
Koyanagi, M.1
Kurino, H.2
Lee, K.-W.3
Sakuma, K.4
Miyakawa, N.5
Itani, H.6
-
2
-
-
85001135329
-
Interchip via technology for vertical system integration
-
P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux, and R. Wieland, "Interchip via technology for vertical system integration," in Proc. IEEE IITC, 2001, pp. 160-162.
-
(2001)
Proc. IEEE IITC
, pp. 160-162
-
-
Ramm, P.1
Bonfert, D.2
Gieser, H.3
Haufe, J.4
Iberl, F.5
Klumpp, A.6
Kux, A.7
Wieland, R.8
-
5
-
-
61549142882
-
3D Integration: Why, what, who, when?
-
J.-Q. Lu, K. Rose, and S. Vitkavage, "3D Integration: Why, what, who, when?" Future Fab Int., no. 23, pp. 25-27, 2007.
-
(2007)
Future Fab Int.
, Issue.23
, pp. 25-27
-
-
Lu, J.-Q.1
Rose, K.2
Vitkavage, S.3
-
6
-
-
70349469833
-
New trends in wafer level packaging
-
N. Sillon, D. Henry, J.-C. Souriau, J. Brun, H. Boutry, and S. Cheramy, "New trends in wafer level packaging," in Proc. IEEE IITC, 2009, pp. 211-213.
-
(2009)
Proc. IEEE IITC
, pp. 211-213
-
-
Sillon, N.1
Henry, D.2
Souriau, J.-C.3
Brun, J.4
Boutry, H.5
Cheramy, S.6
-
7
-
-
62349108063
-
Technologies for 3D wafer level heterogeneous integration
-
M. J. Wolf, P. Ramm, A. Klumpp, and H. Reichl, "Technologies for 3D wafer level heterogeneous integration," in Proc. DTIP MEMS/MOEMS, 2008, pp. 123-126.
-
(2008)
Proc. DTIP MEMS/MOEMS
, pp. 123-126
-
-
Wolf, M.J.1
Ramm, P.2
Klumpp, A.3
Reichl, H.4
-
8
-
-
71049175802
-
Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques
-
002, Oct.
-
Y. Chapuis, A. Debray, L. Jalabert, H. Fujita, and S. Cheramy, "Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques," J. Micromech. Microeng., vol. 19, no. 10, p. 105 002, Oct. 2009.
-
(2009)
J. Micromech. Microeng.
, vol.19
, Issue.10
, pp. 105
-
-
Chapuis, Y.1
Debray, A.2
Jalabert, L.3
Fujita, H.4
Cheramy, S.5
-
9
-
-
51349085624
-
Robust hermetic wafer level thin film encapsulation technology for stacked MEMS/IC package
-
Y. Shimooka, M. Inoue, M. Endo, S. Obata, A. Kojima, T. Miyagi, I. Mori, and H. Shibata, "Robust hermetic wafer level thin film encapsulation technology for stacked MEMS/IC package," in Proc. ECTC, 2008, pp. 824-828.
-
(2008)
Proc. ECTC
, pp. 824-828
-
-
Shimooka, Y.1
Inoue, M.2
Endo, M.3
Obata, S.4
Kojima, A.5
Miyagi, T.6
Mori, I.7
Shibata, H.8
-
10
-
-
70349205855
-
Investigation of key technologies for system-in-package integration of inertial MEMS
-
N. Marenco, W. Reinert, S. Warnat, P. Lange, S. Gruenzig, G. Allegato, G. Hillmann, H. Kostner, W. Gal, S. Guadagnuolo, A. Conte, K. Malecki, and K. Friedel, "Investigation of key technologies for system-in-package integration of inertial MEMS," in Proc. DTIP MEMS/MOEMS, 2009, pp. 35-40.
-
(2009)
Proc. DTIP MEMS/MOEMS
, pp. 35-40
-
-
Marenco, N.1
Reinert, W.2
Warnat, S.3
Lange, P.4
Gruenzig, S.5
Allegato, G.6
Hillmann, G.7
Kostner, H.8
Gal, W.9
Guadagnuolo, S.10
Conte, A.11
Malecki, K.12
Friedel, K.13
-
11
-
-
33646909559
-
New three-dimensional integration technology using self-assembly technique
-
T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New three-dimensional integration technology using self-assembly technique," in IEDM Tech. Dig., 2005, pp. 359-362.
-
(2005)
IEDM Tech. Dig.
, pp. 359-362
-
-
Fukushima, T.1
Yamada, Y.2
Kikuchi, H.3
Koyanagi, M.4
-
12
-
-
50249183988
-
New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique
-
T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, "New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique," in IEDM Tech. Dig., 2007, pp. 985-988.
-
(2007)
IEDM Tech. Dig.
, pp. 985-988
-
-
Fukushima, T.1
Kikuchi, H.2
Yamada, Y.3
Konno, T.4
Liang, J.5
Sasaki, K.6
Inamura, K.7
Tanaka, T.8
Koyanagi, M.9
-
13
-
-
77951604125
-
Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits
-
Apr.
-
T. Fukushima, E. Iwata, T. Konno, J.-C. Bea, K.-W. Lee, T. Tanaka, and M. Koyanagi, "Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits," Appl. Phys. Lett., vol. 96, no. 15, pp. 154 105-1-154 105-3, Apr. 2010.
-
(2010)
Appl. Phys. Lett.
, vol.96
, Issue.15
, pp. 1541051-1541053
-
-
Fukushima, T.1
Iwata, E.2
Konno, T.3
Bea, J.-C.4
Lee, K.-W.5
Tanaka, T.6
Koyanagi, M.7
-
14
-
-
64549128118
-
New heterogeneous multi-chip module integration technology using self-assembly method
-
T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W.-C. Jeong, Y. Ohara, A. Noriki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R. Kobayashi, C.-K. Yin, K. Inamura, K.-W. Lee, J.-C. Bea, T. Tanaka, and M. Koyanagi, "New heterogeneous multi-chip module integration technology using self-assembly method," in IEDM Tech. Dig., 2008, pp. 499-502.
-
(2008)
IEDM Tech. Dig.
, pp. 499-502
-
-
Fukushima, T.1
Konno, T.2
Kiyoyama, K.3
Murugesan, M.4
Sato, K.5
Jeong, W.-C.6
Ohara, Y.7
Noriki, A.8
Kanno, S.9
Kaiho, Y.10
Kino, H.11
Makita, K.12
Kobayashi, R.13
Yin, C.-K.14
Inamura, K.15
Lee, K.-W.16
Bea, J.-C.17
Tanaka, T.18
Koyanagi, M.19
-
15
-
-
70349677328
-
Cu lateral interconnects formed between 100-μm-thick self-assembled chips on flexible substrates
-
M. Murugesan, J.-C. Bea, T. Fukushima, T. Konno, K. Kiyoyama, W.-C. Jeong, H. Kino, A. Noriki, K.-W. Lee, T. Tanaka, and M. Koyanagi, "Cu lateral interconnects formed between 100-μm-thick self-assembled chips on flexible substrates," in Proc. ECTC, 2009, pp. 1496-1501.
-
(2009)
Proc. ECTC
, pp. 1496-1501
-
-
Murugesan, M.1
Bea, J.-C.2
Fukushima, T.3
Konno, T.4
Kiyoyama, K.5
Jeong, W.-C.6
Kino, H.7
Noriki, A.8
Lee, K.-W.9
Tanaka, T.10
Koyanagi, M.11
-
16
-
-
78649678945
-
High-aspect-ratio fine Cu sidewall interconnection over chip edge with tapered polymer for MEMS-LSI multi-chip module
-
A. Noriki, Y. Kaiho, E. Iwata, Y. Ohara, M. Murugesan, K. W Lee, J. C. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, "High-aspect-ratio fine Cu sidewall interconnection over chip edge with tapered polymer for MEMS-LSI multi-chip module," in Proc. Int. Conf. SSDM, 2009, pp. 88-89.
-
(2009)
Proc. Int. Conf. SSDM
, pp. 88-89
-
-
Noriki, A.1
Kaiho, Y.2
Iwata, E.3
Ohara, Y.4
Murugesan, M.5
Lee, K.W.6
Bea, J.C.7
Fukushima, T.8
Tanaka, T.9
Koyanagi, M.10
-
17
-
-
65949104077
-
Development of multi-user multi-chip SOI CMOS-MEMS processes
-
K. Takahashi, M. Mita, M. Nakada, D. Yamane, A. Higo, H. Fujita, and H. Toshiyoshi, "Development of multi-user multi-chip SOI CMOS-MEMS processes," in Proc. MEMS, 2009, pp. 701-704.
-
(2009)
Proc. MEMS
, pp. 701-704
-
-
Takahashi, K.1
Mita, M.2
Nakada, M.3
Yamane, D.4
Higo, A.5
Fujita, H.6
Toshiyoshi, H.7
-
18
-
-
50249134337
-
Integrated MEMS LC resonator with sealed air-suspended structure for single-chip RF LSIs
-
K. Kuwabara, N. Sato, H. Morimura, J. Kodate, M. Nakamura, M. Ugajin, T. Kamei, K. Kudou, K. Machida, and H. Ishii, "Integrated MEMS LC resonator with sealed air-suspended structure for single-chip RF LSIs," in IEDM Tech. Dig., 2007, pp. 423-426.
-
(2007)
IEDM Tech. Dig.
, pp. 423-426
-
-
Kuwabara, K.1
Sato, N.2
Morimura, H.3
Kodate, J.4
Nakamura, M.5
Ugajin, M.6
Kamei, T.7
Kudou, K.8
MacHida, K.9
Ishii, H.10
-
19
-
-
0026851220
-
An innovative bonding technique for optical chips using solder bumps that eliminate chip positioning adjustments
-
Apr.
-
T. Hayashi, "An innovative bonding technique for optical chips using solder bumps that eliminate chip positioning adjustments," IEEE Trans. Compon., Hybrids, Manuf. Technol, vol. 15, no. 2, pp. 225-230, Apr. 1992.
-
(1992)
IEEE Trans. Compon., Hybrids, Manuf. Technol
, vol.15
, Issue.2
, pp. 225-230
-
-
Hayashi, T.1
-
20
-
-
0035278843
-
Microstructure to substrate self-assembly using capillary forces
-
DOI 10.1109/84.911087, PII S1057715701015967
-
U. Srinivasan, D. Liepmann, and R. T. Howe, "Microstructure to substrate self-assembly using capillary forces," J. Microelectromech. Syst., vol. 10, no. 1, pp. 17-24, Mar. 2001. (Pubitemid 32287836)
-
(2001)
Journal of Microelectromechanical Systems
, vol.10
, Issue.1
, pp. 17-24
-
-
Srinivasan, U.1
Liepmann, D.2
Howe, R.T.3
|