Split capacitor DAC mismatch calibration in successive approximation ADC

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 279-282

  Chen, Yanfei ^a   Zhu, Xiaolei ^a   Tamura, Hirotaka ^b   Kibune, Masaya ^b   Tomita, Yasumoto ^b   Hamada, Takayuki ^b   Yoshioka, Masato ^b   Ishikawa, Kiyoshi ^b   Takayama, Takeshi ^b   Ogawa, Junji ^b   Tsukamoto, Sanroku ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION METHOD; CONVENTIONAL DESIGN; INPUT CAPACITANCE; MISMATCH CALIBRATION; OFFSET CANCELLATION; SUCCESSIVE-APPROXIMATION ADC; TIMING CONTROL; TUNABLE CAPACITORS;

APPROXIMATION THEORY; BRIDGES; CALIBRATION; CAPACITORS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MULTICARRIER MODULATION;

CAPACITANCE;

EID: 74049146132     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280859     Document Type: Conference Paper

References (8)

1. D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 264-265, Feb. 2004.
2. B. P. Ginsburg and A. P. Chandrakasan, "Dualscalable 500 MS/s, 5b time-interleaved SAR ADCs for UWB applications," IEEE Custom Integrated Circuits Conference, pp. 403-406, Sep. 2005.
3. N. Verma and A. Chandrakasan, "An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196-1205, Jun. 2007.
4. R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout and Simulation. New York: IEEE Press, 1998.
5. A. Agnes, E. Bonizzoni, P. Malcovati, F. Maloberti, "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," ISSCC Dig. Tech. Papers, pp. 246-610, Feb. 2008.
6. P. M. Figueiredo, et al., "A 90nm CMOS 1.2V 6b 1GS/s two-step subranging ADC," ISSCC Dig. Tech. Papers, pp. 2320-2329, Feb. 2006.
7. V. Giannini, et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic - SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.
8. X. Zhu, et al., "A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology," IEEE Custom Integrated Circuits Conference, pp. 495-498, Sep. 2008.