A workload-adaptive and reconfigurable bus architecture for multicore processors

International Journal of Reconfigurable Computing

Volumn 2010, Issue , 2010, Pages

  Chen, Deming ^a   Akram, Shoaib ^a   Papakonstantinou, Alexandros ^a   Kumar, Rakesh ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCLUSTER COMMUNICATION; INTERCONNECT ARCHITECTURES; INTERCONNECT OPTIMIZATION; MULTI-THREADED APPLICATION; PERFORMANCE SENSITIVITY; RECONFIGURABLE BUS ARCHITECTURES; RECONFIGURABLE INTERCONNECTION NETWORKS; RECONFIGURABLE LOGIC;

INTERCONNECTION NETWORKS; MULTIPROGRAMMING;

MULTICORE PROGRAMMING;

EID: 78349303472     PISSN: 16877195     EISSN: 16877209     Source Type: Journal    
DOI: 10.1155/2010/205852     Document Type: Article

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