-
1
-
-
30844464359
-
The negative bias temperature instability in MOS devices: A review
-
Feb.-Apr.
-
J. H. Stahtis and S. Zafar, "The negative bias temperature instability in MOS devices: A review," Microelectron. Reliab., vol.46, no.2-4, pp. 270-286, Feb.-Apr. 2006.
-
(2006)
Microelectron. Reliab.
, vol.46
, Issue.2-4
, pp. 270-286
-
-
Stahtis, J.H.1
Zafar, S.2
-
2
-
-
67650418339
-
Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks
-
Jun.
-
A. Kerber and E. Cartier, "Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks," IEEE Trans. Device Mater. Rel., vol.9, no.2, pp. 147-162, Jun. 2009.
-
(2009)
IEEE Trans. Device Mater. Rel.
, vol.9
, Issue.2
, pp. 147-162
-
-
Kerber, A.1
Cartier, E.2
-
3
-
-
0041340533
-
Negative bias temperature instability: Road to cross in deep submicron semiconductor manufacturing
-
Jul.
-
D. K. Schroder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron semiconductor manufacturing," Appl. Phys. Lett., vol.94, no.1, pp. 1-18, Jul. 2003.
-
(2003)
Appl. Phys. Lett.
, vol.94
, Issue.1
, pp. 1-18
-
-
Schroder, D.K.1
Babcock, J.A.2
-
4
-
-
0842288263
-
NBTI impact on transistor and circuit: Models, mechanisms and scaling effects
-
A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI impact on transistor and circuit: Models, mechanisms and scaling effects," in IEDM Tech. Dig., 2003, pp. 349-352.
-
(2003)
IEDM Tech. Dig.
, pp. 349-352
-
-
Krishnan, A.T.1
Reddy, V.2
Chakravarthi, S.3
Rodriguez, J.4
John, S.5
Krishnan, S.6
-
5
-
-
0037718399
-
Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics
-
Feb.
-
A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Lett., vol.24, no.2, pp. 87-89, Feb. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.2
, pp. 87-89
-
-
Kerber, A.1
Cartier, E.2
Pantisano, L.3
Degraeve, R.4
Kauerauf, T.5
Kim, Y.6
Hou, A.7
Groeseneken, G.8
Maes, H.E.9
Schwalke, U.10
-
6
-
-
0842309776
-
Universal recovery behavior of negative bias temperature instability
-
S. Rangan, N. Mielke, and E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
-
(2003)
IEDM Tech. Dig.
, pp. 341-344
-
-
Rangan, S.1
Mielke, N.2
Yeh, E.C.C.3
-
7
-
-
56549113808
-
2/TiN gate stacks
-
Nov.
-
2/TiN gate stacks," IEEE Trans. Electron Devices, vol.55, no.11, pp. 3175-3183, Nov. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.11
, pp. 3175-3183
-
-
Kerber, A.1
Maitra, K.2
Majumdar, A.3
Hargrove, M.4
Carter, R.J.5
Cartier, E.6
-
8
-
-
77957919160
-
PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks
-
K. Zhao, J. H. Stathis, A. Kerber, and E. Cartier, "PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks," in Proc. IRPS, 2010, pp. 50-54.
-
Proc. IRPS
, vol.2010
, pp. 50-54
-
-
Zhao, K.1
Stathis, J.H.2
Kerber, A.3
Cartier, E.4
-
9
-
-
34247847473
-
Analysis of NBTI degradation-and recovery-behavior based on ultra fast v T-measurements
-
H. Reisinger, O. Blank, W. Heinrigs, A. Mühlhoff, W. Gustin, and C. Schlünder, "Analysis of NBTI degradation-and recovery-behavior based on ultra fast V T-measurements," in Proc. IRPS, 2006, pp. 448-453.
-
(2006)
Proc. IRPS
, pp. 448-453
-
-
Reisinger, H.1
Blank, O.2
Heinrigs, W.3
Mühlhoff, A.4
Gustin, W.5
Schlünder, C.6
-
10
-
-
51549107155
-
BTI reliability of 45 nm high-k + metal-gate process technology
-
S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, "BTI reliability of 45 nm high-k + metal-gate process technology," in Proc. IRPS, 2008, pp. 352-357.
-
(2008)
Proc. IRPS
, pp. 352-357
-
-
Pae, S.1
Agostinelli, M.2
Brazier, M.3
Chau, R.4
Dewey, G.5
Ghani, T.6
Hattendorf, M.7
Hicks, J.8
Kavalieros, J.9
Kuhn, K.10
Kuhn, M.11
Maiz, J.12
Metz, M.13
Mistry, K.14
Prasad, C.15
Ramey, S.16
Roskowski, A.17
Sandford, J.18
Thomas, C.19
Thomas, J.20
Wiegand, C.21
Wiedemer, J.22
more..
-
11
-
-
37148999689
-
Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study
-
Dec.
-
K. Maitra, M. M. Frank, V. Narayanan, V. Misra, and E. Cartier, "Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study," J. Appl. Phys., vol.102, no.11, p. 114507, Dec. 2007.
-
(2007)
J. Appl. Phys.
, vol.102
, Issue.11
, pp. 114507
-
-
Maitra, K.1
Frank, M.M.2
Narayanan, V.3
Misra, V.4
Cartier, E.5
-
12
-
-
0033280060
-
The impact of bias tempera e instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling
-
N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, "The impact of bias tempera e instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," in VLSI Symp. Tech. Dig., 1999, pp. 73-74.
-
(1999)
VLSI Symp. Tech. Dig.
, pp. 73-74
-
-
Kimizuka, N.1
Yamamoto, T.2
Mogami, T.3
Yamaguchi, K.4
Imai, K.5
Horiuchi, T.6
-
13
-
-
40549122135
-
Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation
-
Sep.
-
A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, "Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation," IEEE Trans. Electron Devices, vol.54, no.9, pp. 2143-2154, Sep. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.9
, pp. 2143-2154
-
-
Islam, A.E.1
Kufluoglu, H.2
Varghese, D.3
Mahapatra, S.4
Alam, M.A.5
-
14
-
-
3042607843
-
Hole trapping effect on methodology or DC and AC negative bias temperature instability measurements in PMOS transistors
-
V. Huard and M. Denais, "Hole trapping effect on methodology or DC and AC negative bias temperature instability measurements in PMOS transistors," in Proc. IRPS, 2004, pp. 40-45.
-
(2004)
Proc. IRPS
, pp. 40-45
-
-
Huard, V.1
Denais, M.2
|