메뉴 건너뛰기




Volumn , Issue , 2010, Pages 94-97

Modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs

Author keywords

Device simulation; Gate length; Plasma induced damage; Recess structure; Subthreshold leakage; Threshold voltage

Indexed keywords

DEVICE SIMULATIONS; GATE LENGTH; PLASMA-INDUCED DAMAGE; RECESS STRUCTURE; SUB-THRESHOLD LEAKAGE;

EID: 77955597364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2010.5510280     Document Type: Conference Paper
Times cited : (5)

References (14)
  • 2
    • 1542605495 scopus 로고    scopus 로고
    • Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-?m CMOS
    • S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan, "Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-?m CMOS," IEEE J. Solid-State Circuits, vol. 39, pp. 501-510, 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , pp. 501-510
    • Narendra, S.1    De, V.2    Borkar, S.3    Antoniadis, D.A.4    Chandrakasan, A.P.5
  • 5
    • 33646864552 scopus 로고    scopus 로고
    • Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits
    • K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. IEEE, vol. 91, pp. 305-327, 2003.
    • (2003) Proc. IEEE , vol.91 , pp. 305-327
    • Roy, K.1    Mukhopadhyay, S.2    Mahmoodi-Meimand, H.3
  • 6
    • 77950335052 scopus 로고    scopus 로고
    • Metrology of line-edge roughness: Impact on device performance
    • A. Yamaguchi, H. Kawada, and T. Izumi, "Metrology of line-edge roughness: Impact on device performance," Proc. Symp. Dry Process, pp. 277-278, 2007.
    • (2007) Proc. Symp. Dry Process , pp. 277-278
    • Yamaguchi, A.1    Kawada, H.2    Izumi, T.3
  • 7
    • 36248933153 scopus 로고    scopus 로고
    • A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    • H. F. Dadgour, L. Sheng-Chih, and K. Banerjee, "A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations," IEEE Trans. Electron Devices, vol. 54, pp. 2930-2945, 2007.
    • (2007) IEEE Trans. Electron Devices , vol.54 , pp. 2930-2945
    • Dadgour, H.F.1    Sheng-Chih, L.2    Banerjee, K.3
  • 8
  • 11
    • 77952696058 scopus 로고    scopus 로고
    • Model for Bias Frequency Effects on Plasma-Damaged Layer Formation in Si Substrate
    • to be published
    • K. Eriguchi, Y. Nakakubo, A. Matsuda, Y. Takao, and K. Ono, "Model for Bias Frequency Effects on Plasma-Damaged Layer Formation in Si Substrate," to be published in Jpn. J. Appl. Phys., 2010.
    • (2010) Jpn. J. Appl. Phys.
    • Eriguchi, K.1    Nakakubo, Y.2    Matsuda, A.3    Takao, Y.4    Ono, K.5
  • 12
    • 34548135181 scopus 로고
    • Calculations of nuclear stopping, ranges, and straggling in the low-energy region
    • W. D. Wilson, L. G. Haggmark, and J. P. Biersack, "Calculations of nuclear stopping, ranges, and straggling in the low-energy region," Phys. Rev. B, vol. 15, p. 2458, 1977.
    • (1977) Phys. Rev. B , vol.15 , pp. 2458
    • Wilson, W.D.1    Haggmark, L.G.2    Biersack, J.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.