Effects of plasma-induced Si recess structure on n-MOSFET performance degradation

IEEE Electron Device Letters

Volumn 30, Issue 7, 2009, Pages 712-714

  Eriguchi, Koji ^a   Matsuda, Asahiko ^a   Nakakubo, Yoshinori ^a   Kamei, Masayuki ^a   Ohta, Hiroaki ^a   Ono, Kouichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Device simulation; MOSFETs; Plasma induced damage (PID); Recess structure; Threshold voltage

Indexed keywords

ANALYTICAL MODEL; DEVICE SIMULATION; DEVICE SIMULATIONS; GAS PLASMA; GATE LENGTH; LINEAR RELATIONSHIPS; MOSFETS; NMOSFET; NMOSFETS; OFF-STATE LEAKAGE CURRENT; OFFSET SPACERS; PERFORMANCE DEGRADATION; PLASMA DAMAGE; PLASMA-INDUCED; PLASMA-INDUCED DAMAGE (PID); RECESS STRUCTURE; THRESHOLD VOLTAGE SHIFTS;

DEGRADATION; MOSFET DEVICES; PLASMAS; PROPORTIONAL CONTROL SYSTEMS; SILICON; SIMULATORS; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 67650421492     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2022347     Document Type: Article

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