Statistical leakage modeling in CMOS logic gates considering process variations

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 301-304

  D'Agostino, Carmelo ^a   Flatresse, Philippe ^a   Beigne, Edith ^b   Belleville, Marc ^b  

^a STMICROELECTRONICS   (Italy)

^b CEA LETI   (France)

Author keywords

Leakage current; Process variation; Statistical analysis

Indexed keywords

ANALYSIS METHODS; AND MODELING; CMOS LOGIC GATES; CMOS TECHNOLOGIES; IC DESIGNS; IN-PROCESS; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; LEAKAGE CURRENT; LEAKAGE POWER; MONTE-CARLO SIMULATIONS; PROCESS VARIATION; PROCESS VARIATIONS; SCALED CMOS; ST MICROELECTRONICS; STATISTICAL ANALYSIS; STATISTICAL LEAKAGE; STATISTICAL PROCESS VARIATIONS; SUB THRESHOLDS; VERILOG-A;

CMOS INTEGRATED CIRCUITS; DIFFERENCE EQUATIONS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC DEVICES; LOGIC GATES; SIMULATORS; STATISTICAL METHODS; TECHNOLOGY;

PROCESS ENGINEERING;

EID: 50849142433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567301     Document Type: Conference Paper

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