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Volumn , Issue , 2010, Pages 341-345

Window optimization of reversible and quantum circuits

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SCENARIO; EMERGING TECHNOLOGIES; LOW-POWER DESIGN; QUANTUM CIRCUIT; QUANTUM COMPUTATION; SUB-CIRCUITS;

EID: 77954902983     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2010.5491754     Document Type: Conference Paper
Times cited : (30)

References (19)
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    • Desoete, B.1    Vos, A.D.2
  • 4
    • 0043136670 scopus 로고    scopus 로고
    • A transformation based algorithm for reversible logic synthesis
    • D. M. Miller, D. Maslov, and G. W. Dueck, "A transformation based algorithm for reversible logic synthesis," in Design Automation Conf., 2003, pp. 318-323.
    • (2003) Design Automation Conf. , pp. 318-323
    • Miller, D.M.1    Maslov, D.2    Dueck, G.W.3
  • 5
    • 4444239912 scopus 로고    scopus 로고
    • A new heuristic algorithm for reversible logic synthesis
    • P. Kerntopf, "A new heuristic algorithm for reversible logic synthesis," in Design Automation Conf., 2004, pp. 834-837.
    • (2004) Design Automation Conf. , pp. 834-837
    • Kerntopf, P.1
  • 6
    • 33750588847 scopus 로고    scopus 로고
    • An algorithm for synthesis of reversible logic circuits
    • P. Gupta, A. Agrawal, and N. K. Jha, "An algorithm for synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 25, no. 11, pp. 2317-2330, 2006.
    • (2006) IEEE Trans. on CAD , vol.25 , Issue.11 , pp. 2317-2330
    • Gupta, P.1    Agrawal, A.2    Jha, N.K.3
  • 7
    • 50449107078 scopus 로고    scopus 로고
    • Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares
    • D. Große, R. Wille, G. W. Dueck, and R. Drechsler, "Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares," in Int'l Symp. on Multi-Valued Logic, 2008, pp. 214-219.
    • (2008) Int'l Symp. on Multi-Valued Logic , pp. 214-219
    • Große, D.1    Wille, R.2    Dueck, G.W.3    Drechsler, R.4
  • 9
    • 65349142610 scopus 로고    scopus 로고
    • Exact multiple control toffoli network synthesis with SAT techniques
    • D. Große, R. Wille, G. W. Dueck, and R. Drechsler, "Exact multiple control Toffoli network synthesis with SAT techniques," IEEE Trans. on CAD, vol. 28, no. 5, pp. 703-715, 2009.
    • (2009) IEEE Trans. on CAD , vol.28 , Issue.5 , pp. 703-715
    • Große, D.1    Wille, R.2    Dueck, G.W.3    Drechsler, R.4
  • 10
    • 20444459774 scopus 로고    scopus 로고
    • Toffoli network synthesis with templates
    • D. Maslov, G. W. Dueck, and D. M. Miller, "Toffoli network synthesis with templates," IEEE Trans. on CAD, vol. 24, no. 6, pp. 807-817, 2005.
    • (2005) IEEE Trans. on CAD , vol.24 , Issue.6 , pp. 807-817
    • Maslov, D.1    Dueck, G.W.2    Miller, D.M.3
  • 15
    • 25544459735 scopus 로고
    • Reversible logic and quantum computers
    • A. Peres, "Reversible logic and quantum computers," Phys. Rev. A, no. 32, pp. 3266-3276, 1985.
    • (1985) Phys. Rev. A , vol.32 , pp. 3266-3276
    • Peres, A.1
  • 16
    • 84978092325 scopus 로고
    • Reversible computing
    • W. de Bakker and J. van Leeuwen, Eds. Springer technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci.
    • T. Toffoli, "Reversible computing," in Automata, Languages and Programming, W. de Bakker and J. van Leeuwen, Eds. Springer, 1980, p. 632, technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci.
    • (1980) Automata, Languages and Programming , pp. 632
    • Toffoli, T.1
  • 17
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    • RevLib: An online resource for reversible functions and reversible circuits
    • is available at
    • R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, "RevLib: an online resource for reversible functions and reversible circuits," in Int'l Symp. on Multi-Valued Logic, 2008, pp. 220-225, RevLib is available at http://www.revlib.org.
    • (2008) Int'l Symp. on Multi-Valued Logic , pp. 220-225
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  • 19
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    • Reversible logic synthesis with output permutation
    • R. Wille, D. Große, G. Dueck, and R. Drechsler, "Reversible logic synthesis with output permutation," in VLSI Design, 2009, pp. 189-194.
    • (2009) VLSI Design , pp. 189-194
    • Wille, R.1    Große, D.2    Dueck, G.3    Drechsler, R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.