Subthreshold source-coupled logic circuits for ultra-low-power applications

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 7, 2008, Pages 1699-1710

  Tajalli, Armin ^a,b   Brauer, Elizabeth J ^a,c   Leblebici, Yusuf ^a,b   Vittoz, Eric ^a,b  

^a IEEE

^b EPFL   (Switzerland)

^c Northern Arizona University   (United States)

Author keywords

CMOS integrated circuits; CMOS logic circuit; Current mode logic (CML); Pipelining; Power delay product; Source coupled logic (SCL); Subthreshold CMOS; Subthreshold SCL; Ultra low power circuits; Weak inversion

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; ELECTRIC NETWORK TOPOLOGY; FUZZY LOGIC; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING THEORY; TOPOLOGY;

(P ,P ,T) MEASUREMENTS; CIRCUIT TOPOLOGIES; CMOS TECHNOLOGIES; DIGITAL BLOCKS; DIGITAL COMPONENTS; FREQUENCY DIVIDER (FD); FUNDAMENTAL CIRCUITS; HIGH RESISTIVITY (HR); MINIMUM SIZE; NOVE L APPROACH; OPERATION FREQUENCIES; ORDERS-OF-MAGNITUDE; PARALLEL MULTIPLIERS; PMOS TRANSISTORS; POWER CONSUMPTION (CE); POWER DELAYS; RING OSCILLATORS; SOURCE COUPLED LOGIC (SCL) GATES; SOURCE-COUPLED LOGIC (SCL); SUB THRESHOLDS; SUBTHRESHOLD CMOS CIRCUITS; SUPPLY VOLTAGES; ULTRA LOW POWER (ULP); WEAK INVERSIONS; WIDE-RANGE;

LOGIC CIRCUITS;

EID: 46749108096     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.922709     Document Type: Conference Paper

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