메뉴 건너뛰기




Volumn , Issue , 2008, Pages 145-148

Improving the power-delay product in SCL circuits using source follower output stage

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; TECHNICAL PRESENTATIONS;

EID: 51749085103     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541375     Document Type: Conference Paper
Times cited : (9)

References (10)
  • 1
    • 25144514874 scopus 로고    scopus 로고
    • Modeling and sizing for minimum energy operation in subthreshold circuits
    • Sep
    • B. H. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.9 , pp. 1778-1786
    • Calhoun, B.H.1    Wang, A.2    Chandrakasan, A.3
  • 2
    • 31344455697 scopus 로고    scopus 로고
    • Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering
    • Jan
    • B. H. Calhoun, and A. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238-245, Jan. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.1 , pp. 238-245
    • Calhoun, B.H.1    Chandrakasan, A.2
  • 3
    • 1242263410 scopus 로고    scopus 로고
    • A micropower programmable DSP using approximate signal processing based on distributed arithmatic
    • Feb
    • R. Amirtharajah, and A. Chandrakasan, "A micropower programmable DSP using approximate signal processing based on distributed arithmatic," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 337-347, Feb. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.2 , pp. 337-347
    • Amirtharajah, R.1    Chandrakasan, A.2
  • 5
    • 44849114467 scopus 로고    scopus 로고
    • Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept
    • Munich, Germany, Sep
    • A. Tajalli, E. Vittoz, Y. Leblebici, and E. J. Brauer, "Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept," in Proc. of Eur. Solid-State Cir. Conf. (ESSCIRC), Munich, Germany, Sep. 2007, pp. 281-284.
    • (2007) Proc. of Eur. Solid-State Cir. Conf. (ESSCIRC) , pp. 281-284
    • Tajalli, A.1    Vittoz, E.2    Leblebici, Y.3    Brauer, E.J.4
  • 6
    • 33846258717 scopus 로고    scopus 로고
    • A low-power integrated circuit for a wireless 100-electrode neural recording system
    • Jan
    • R.R. Harrison, and et al., "A low-power integrated circuit for a wireless 100-electrode neural recording system," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 123-133, Jan. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.1 , pp. 123-133
    • Harrison, R.R.1    and et, al.2
  • 7
    • 34548851757 scopus 로고    scopus 로고
    • Breaking the power-delay tradeoff: Design of low-power high-speed MOS current-mode logic circuits operating with reduced supply voltage
    • ISCAS, pp, May
    • S. Badel and Y. Leblebici, "Breaking the power-delay tradeoff: design of low-power high-speed MOS current-mode logic circuits operating with reduced supply voltage," in Proc. of IEEE Int. Symp. on Circ. and Syst. (ISCAS), pp. 1871-1874, May 2007.
    • (2007) Proc. of IEEE Int. Symp. on Circ. and Syst , pp. 1871-1874
    • Badel, S.1    Leblebici, Y.2
  • 10
    • 33846353150 scopus 로고    scopus 로고
    • Power-aware design techniques for nanometer MOS current-mode logic gates: A design framework
    • M. Alioto, G. Palumbo, "Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework," IEEE Circ. and Syst. Magazine, vol. 6, no. 4, pp. 40-59, 2006.
    • (2006) IEEE Circ. and Syst. Magazine , vol.6 , Issue.4 , pp. 40-59
    • Alioto, M.1    Palumbo, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.