Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2010, Pages 194-199

  Shamshiri, Saeed ^a   Cheng, Kwang Ting ^a  

^a University of California   (United States)

Author keywords

NoC; Non uniform spare distributtion; Quality analysis; SoC; Yield and cost modeling

Indexed keywords

COST MODELING; COST-EFFICIENT; DISTRIBUTED REDUNDANCY; MESH-BASED NOC; MULTICORE CHIPS; NON-UNIFORM DISTRIBUTION; NONUNIFORM; OVERALL QUALITY; QUALITY ANALYSIS; QUALITY CONSTRAINTS; QUALITY METRICES;

COSTS; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY CONTROL;

COST BENEFIT ANALYSIS;

EID: 77953890052     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2010.5469579     Document Type: Conference Paper

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