An error-oriented test methodology to improve yield with error-tolerance

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 130-135

  Hsieh, Tong Yu ^a   Lee, Kuen Jong ^a   Breuer, Melvin A ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DIGITAL CIRCUITS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; VLSI CIRCUITS;

DEFECTIVE CHIPS; ERROR-TOLERANCE; TEST PATTERNS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 33751114448     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.18     Document Type: Conference Paper

References (6)

1. Int'l Technology Roadmap for Semiconductors (ITRS), 2003, http://public.itrs.net/files/2003itrs/home2003.htm.
2. M. A. Breuer, S. K. Gupta and T. M. Mak, "Defect and error-tolerance in the presence of massive numbers of defects," IEEE Design & Test of Computers, 21(3), pp. 216-227, 2004.
3. M. A. Breuer, "Intelligible test techniques to support error-tolerance," Asian Test Symposium, pp. 386-393, 2004.
4. K. J. Lee, T. Y. Hsieh and M. A. Breuer, "A novel test methodology based on error-rate to support error-tolerance," Int'l Test Conf., pp. 1136-1144, 2005.
5. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing: for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
6. S. Ghahramani, Fundamentals of Probability 2/P, Prentice Hall, 2000.