Truncated binary multipliers with variable correction and minimum mean square error

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 6, 2010, Pages 1312-1325

  Petra, Nicola ^a   De Caro, Davide ^a   Garofalo, Valeria ^a   Napoli, Ettore ^a   Strollo, Antonio G M ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

Digital arithmetic; Error analysis; Error compensation; Least mean square method; Multiplication; Truncated multipliers

Indexed keywords

BINARY MULTIPLIERS; CLOSED FORM; COMPENSATION FUNCTIONS; HARDWARE IMPLEMENTATIONS; LEAST MEAN SQUARE METHOD; MINIMUM MEAN SQUARE ERRORS; MULTIPLICATION; OPTIMAL FUNCTION; TRUNCATED MULTIPLIERS;

BLOCK CODES; DIGITAL ARITHMETIC; ERROR ANALYSIS; HARDWARE; HARMONIC ANALYSIS; MEAN SQUARE ERROR; OPTIMIZATION;

ERROR COMPENSATION;

EID: 77953291373     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2033536     Document Type: Article

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