A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

IEEE Transactions on Computers

Volumn 45, Issue 3, 1996, Pages 294-306

  Oklobdzija, Vojin G ^a,b,c   Villeger, David ^d   Liu, Simon S ^e  

^a IEEE

^b Integration   (United States)

^c Davis   (United States)

^d Ecole Superieure d'Ingenieurs en   (France)

^e ADVANCED MICRO DEVICES   (United States)

Author keywords

3:2 counter; 4:2 adder; Array multiplier; Booth encoding; Dadda's counter; Parallel multiplier; Partial product reduction; VLSI arithmetic; Wallace tree

Indexed keywords

EID: 17644373718     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.485568     Document Type: Article

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