Area-efficient multipliers for digital signal processing applications

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 2, 1996, Pages 90-95

  Kidambi, Sunder S ^a   El Guibaly, Payez ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL ARITHMETIC; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; ERRORS; LOGIC GATES; PARAMETER ESTIMATION; PROBABILITY; SIGNAL TO NOISE RATIO; STATISTICS; VLSI CIRCUITS;

AREA EFFICIENT PARALLEL MULTIPLIER; ARRAY OF FULL ADDERS; PROBABILISTIC ESTIMATION; QUANTIZATION ERROR; TRUNCATED MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 0030083958     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.486455     Document Type: Article

References (10)

1. S. Waser and M. J. Flyim, Introduction to Arithmetic for Digital Systems Designers. New York: CBS Collège Publ., 1982.
2. J. J. F. Cavanagh, Digital Computer Arithmetic. New York; McGrawHul, 1984.
3. M. Hatamian and O. L. Cash, "A 70-MHr 8 x 8-bit parallel pipelined multiplier in 2.5 μm CMOS," IEEE J. Solùl-Slale Circuits, vol. SC21, pp. 505-513, Aug. 1986.
4. T. G. Noll, D. Schmitt-Landsieclel, and G. Enders, "A pipelined 330MHz multiplier," 1EEEJ. Solid-State Circuit, vol. SC21, pp. 411-416, June 1986.
5. D. A. Henlin, M. T. Feilsch, M. Mazin, and E. D. Lewis, "A 16 bit X 16 bit pipelined multiplier macrocell," IEEE J. Solid-State Circuits, vol. SC20, pp. 542-547, Apr. 1935.
6. [6J C. P. Lerouge, P. Girard, and J. S. Colardelle, "A fast 16 bit NMOS parallel multiplier," IEEE J. Solid-Slate Circuits, vol. SC19, pp. 338-342, June 1984.
7. D. G. Ciawley aBd G. A. J. Amaratunga, "8 x 8 bit pipelined Dadda multiplier in CMOS," IEE Proc., vol. 135, Pt. G, pp. 231-240, Dec. 1988.
8. S. Nakamura and K.-Y. Chu, "A single chip parallel multiplier by MOS technology," IEEE Trans. Comput., vol. 37, pp. 274-282, Mar. 1988.
9. A. Antoniou. Digital Fillers: Analysis, Design, and Applications, 2nd ed. New York: McGraw-Hill, 1993.
10. C. R. Baugh and B. A. Wooley, "A two's complement parallel array multiplication algorithm," IEEE Trans. Comput., vol. C22, pp. 1045-1047, Dec. 1973.