Design of the lower error fixed-width multiplier and its application

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 10, 2000, Pages 1112-1118

  Wang, Shuenn Shyang ^a   Feng, Wu Shiung ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; ERROR COMPENSATION; FIR FILTERS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; SPEECH PROCESSING; VLSI CIRCUITS;

FIXED WIDTH MULTIPLIER; GENERALIZED INDEX; TRUNCATION ERROR;

MULTIPLYING CIRCUITS;

EID: 0034296236     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.877155     Document Type: Article

References (9)

1. S. Y. Kung, VLSI Array Processors. Englewood Cliffs, NJ: Prentice-Hall, 1988.
2. S. L. Freeny Special-purpose hardware for digital filtering," Proc. IEEE, vol. 63, pp. 633-647, Apr. 1975.
3. L. D. Van, C. C. Tang, S. Tengchen, and W. S. Feng A new VLSI architecture without global broadcast for 2-D digital filters," in Proc. IEEE Int. Symp. Circuits Systems, Geneva, Switzerland, May 2000, pp. 547-550.
4. K. Hwang, Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
5. F. Cavanagh, Digital Computer Arithmetic: Design and Implementation. New York: McGraw-Hill, 1984.
6. S. S. Kidambi, F El-Guibaly, and A. Antoniou Area-efficient multipliers for digital signal processing applications," IEEE Trans. Circuits Syst. II, vol. 43, pp. 90-94, Feb. 1996.
7. J. M. Jou and S. R. Kuang Design of a low-error fixed-width multiplier for DSP applications," Electron. Lett., vol. 33, no. 19, pp. 1597-1598, 1997.
8. M. E. Paul and K. Bruce, C Language Algorithms for Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1991.
9. L. D. Van, S. S. Wang, S. Tengchen, W. S. Feng, and B. S. Jeng Design of a lower error fixed-width multiplier for speech processing application," Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, pp. 130-133, May 1999.