Truncated multiplication with approximate rounding

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

Volumn 2, Issue , 1999, Pages 1480-1483

  Swartzlander, E E ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC OPERATIONS; DATA YIELDS; SIGNAL PROCESSING APPLICATIONS; TRUNCATED MULTIPLICATION;

SIGNAL PROCESSING; COMPUTATION THEORY;

DIGITAL ARITHMETIC; SIGNAL PROCESSING;

ROUNDED MULTIPLICATION; TRUNCATED MULTIPLICATION;

EID: 0033325364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.1999.831996     Document Type: Conference Paper

References (7)

1. C.R. Baugh and B. A. Wooley, "A Twos Complement Paranel-Array Multiplication Algorithm, " IE E E Transactions on Computers, Vol. C-22, 1973, pp. 1045-1047.
2. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, New York: Oxford University Press, 2000
3. M. D. Ercegovac and T. Lang, Division and Square Root: Digit Recurrence Algorithms and Implementations, Boston: Kluwer Academic Publishers, 1994
4. Y. C. Lim, "Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications, " IEEE Transactions on Computers, vol. 41, 1992, pp. 1333-1336.
5. M. J. Schulte and E. E. Swartzlander, Jr. "Truncated Multiplication with Correction Constant, " VLSZ Signal Processing, VI, New York, IEEE Press, 1993, pp. 388-396.
6. E. J. King and E. E. Swartzlander, Jr. "Data-Dependent Truncation Scheme for Parallel Multipliers, " 31 st Asilomar Conference on Signals, Circuits and Systems, Pacific Grove, CA, 1997, pp. 1178-1182.
7. M. J. Schulte, J. E. Stine and J. G. Jansen, "Reduced Power Dissipation Through Truncated Multiplication" IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como, Italy, 1999, pp. 61-69.