Truncated multiplication with symmetric correction

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2006, Pages 931-934

  Park, Hyuk ^a   Swartzlander Jr , Earl E ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRECTION METHODS; DIGITAL SIGNAL PROCESSING SYSTEMS; ERROR PATTERNS; PARALLEL MULTIPLIERS; POWER DISSIPATIONS; TRUNCATED MULTIPLICATION;

DIGITAL SIGNAL PROCESSING; ELECTROMAGNETIC WAVE ATTENUATION; ERROR CORRECTION; ERRORS; SIGNAL PROCESSING;

PARALLEL PROCESSING SYSTEMS;

EID: 47049118490     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2006.354887     Document Type: Conference Paper

References (11)

1. G. K. Ma and F. J. Tayor, "Multiplier Policies for Digital Signal Processing," IEEE ASSP Magazine, Vol. 7, no. 1, pp. 6-20, 1990.
2. L. Dadda, "Some Schemes for Parallel Multiplier," Alta Frequenza, Vol. 34, pp. 349-356, 1965.
3. C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Transactions on Electronic Computers, Vol. 13, pp. 14-17, 1964.
4. K. Bicherstaff, M. J. Schulte, and E. E. Swartzlander, Jr., "Parallel Reduced Area Multipliers," Journal of VLSI Signal Processing, Vol. 9, pp. 181-191, 1995.
5. S. S. Mahant-Shetti, P. T. Balsara, and C. Lemonds, "High Performance Low Power Array Multiplier Using Temporal Tiling ," IEEE Transactions on VLSI Systems, Vol. 7, pp. 121-124, 1999.
6. S. D. Pezaris, "A 40-ns 17-Bit by 17-Bit Array Multiplier," IEEE Transactions on Computers, Vol. 20, pp. 442-447, 1971.
7. Y C. Lim, "Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications," IEEE Transactions on Computers, Vol. 41, pp. 1333-1336, 1992.
8. M. J. Schulte and E. E. Swartzlander, Jr., "Truncated Multiplication with Correction Constant," VLSI Signal Processing, VI, New York, IEEE Press, pp. 388-396, 1993.
9. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, "Area-Efficient Multipliers for Digital Signal Processing Applications," IEEE Transactions on Circuits and Systems. II, Vol. 43, pp. 90-94, 1996.
10. E. J. King and E. E. Swartzlander, Jr., "Data-Dependent Truncation Scheme for Parallel Multipliers," 31st Asilomar Conference on Signals, Circuits and Systems, Pacific Grove, CA, pp. 1178-1182, 1997.
11. E. E. Swartzlander, Jr., "Truncated Multiplication with Approximate Rounding," Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems and Computers, pp. 1480-1483, 1999.