A novel bottom spacer FinFET structure for improved short-channel, power-delay, and thermal performance

IEEE Transactions on Electron Devices

Volumn 57, Issue 6, 2010, Pages 1287-1294

  Shrivastava, Mayank ^a   Baghini, Maryam Shojaei ^a   Sharma, Dinesh Kumar ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Bulk fin shaped field effect transistor (FinFET); Electrothermal; Fin shaped field effect transistor (FinFET); Self heating; Short channel performance; Spacer; Width quantization

Indexed keywords

ELECTRO-THERMAL SIMULATION; FIELD-EFFECT; FINFETS; LOGIC APPLICATIONS; MODE SIMULATION; POWER DISSIPATION; PROCESS STEPS; SELF-HEATING; SHORT-CHANNEL PERFORMANCE; SILICON ON INSULATOR; SOC APPLICATION; SYSTEM-ON-CHIP; THERMAL PERFORMANCE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; HEATING; PROGRAMMABLE LOGIC CONTROLLERS;

FINS (HEAT EXCHANGE);

EID: 77952742597     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2045686     Document Type: Article

References (16)

1. J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, and H.-S. P. Wong, "Fabrication of metal gated FinFETs through complete gate silicidation with Ni," IEEE Trans. Electron Devices, vol.51, no.12, pp. 2115-2120, Dec. 2004.
2. A. B. Sachid, R. Francis, M. S. Baghini, D. K. Sharma, K.-H. Bach, R. Mahnkopf, and V. R. Rao, "Sub-20 nm gate length FinFET design: Can high-? Spacers make a difference?," in IEDM Tech. Dig., 2008, pp. 697-700.
3. M. Shrivastava, M. S. Baghini, D. K. Sharma, andV.R.Rao, "Anovel and robust approach for common mode feedback using IDDG FinFET," IEEE Trans. Electron Devices, vol.55, no.11, pp. 3274-3282, Dec. 2008.
4. R. Thakkar, M. Shrivastava, M. S. Baghini, D. K. Sharma, K.-H. Bach, R. Mahnkopf, and V. R. Rao, "A novel architecture for improving slew rate in FinFET-based Op-Amps and OTAs," IEEE Trans. Electron Devices, to be published.
5. A. B. Sachid, M. Shrivastava, R. A. Thakkar,M. S.Baghini, D. K. Sharma, M. B. Patil, and V. R. Rao, "Technology-aware design (TAD) for sub-45 nm CMOS technologies," in Proc. Intel Asia Academic Forum, Taipei, Taiwan, Oct. 20-22, 2008.
6. C. R. Manoj, N. Meenakshi, V. Dhanya, and V. R. Rao, "Device design & optimization considerations for bulk FinFETs," IEEE Trans. Electron Devices, vol.55, no.2, pp. 609-615, Feb. 2008.
7. T.-S. Park, H. J. Cho, J. D. Choe, S. Y. Han, D. Park, K. Kim, E. Yoon, and J.-H. Lee, "Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)," IEEE Trans. Electron Devices, vol.53, no.3, pp. 481-487, Mar. 2006.
8. K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima, and H. Ishiuchi, "Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length," in IEDM Tech. Dig., 2008, pp. 721-724.
9. J. Gu, J. Keane, S. Sapatnekar, and C. Kim, "Width quantization aware FinFET circuit design," in Proc. IEEE CICC, 2006, pp. 337-340.
10. Sentaurus Structure Editor, Version Z-2007.03, Mar. 2007.
11. S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol.50, no.11, pp. 2255-2261, Nov. 2003.
12. Sentaurus Device User Guide, Synopsys, Inc., Mountain View, CA, Version Z-2007.03, Mar. 2007.
13. M. Shrivastava, B. Verma, M. S. Baghini, C. Russ, D. K. Sharma, H. Gossner, and V. R. Rao, "Benchmarking the device performance at sub 22 nm node technologies using an SoC framework," in IEDM Tech. Dig., 2009, pp. 505-508.
14. K. von Arnim, E. Augendre, A. C. Pacha, T. Schulz, K. T. San, F. Bauer, A. Nackaerts, R. Rooyackers, T. Vandeweyer, B. Degroote, N. Collaert, A. Dixit, R. Singanamalla, W. Xiong, A. Marshall, C. R. Cleavelin, K. Schrufer, and M. Jurczak, "A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM," in VLSI Symp. Tech. Dig., 2007, pp. 106-107.
15. T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, and D. Flandre, "Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode," Microelectron. Eng., vol.80, pp. 386-389, Jun. 2005.
16. R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, R. J. Luyken, W. Rösner, and M. Städele, "Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results," Microelectron. Eng., vol.83, no.2, pp. 241-246, Feb. 2006.