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Volumn , Issue , 2006, Pages 337-340

Width quantization aware FinFET circuit design

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC LOGIC CIRCUITS; FINFET DEVICES; WIDTH QUANTIZATION;

EID: 34547350738     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320916     Document Type: Conference Paper
Times cited : (32)

References (8)
  • 1
    • 10644230219 scopus 로고    scopus 로고
    • Fabrication of metal gated FinFETs through complete gate silicidation with Ni
    • J. Kedzierski, M. Ieong; T. Kanarsky, et al., "Fabrication of metal gated FinFETs through complete gate silicidation with Ni," IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2115-2120, 2004.
    • (2004) IEEE Transactions on Electron Devices , vol.51 , Issue.12 , pp. 2115-2120
    • Kedzierski, J.1    Ieong, M.2    Kanarsky, T.3
  • 3
    • 1842865629 scopus 로고    scopus 로고
    • Turning silicon on its edge [double gate CMOS/FinFET technology]
    • E. J. Nowak, I. Aller, T. Ludwig, K. Kim, et al., "Turning silicon on its edge [double gate CMOS/FinFET technology]," IEEE Circuits and Devices Magazine, vol. 20, no.1, pp. 20-31, 2004.
    • (2004) IEEE Circuits and Devices Magazine , vol.20 , Issue.1 , pp. 20-31
    • Nowak, E.J.1    Aller, I.2    Ludwig, T.3    Kim, K.4
  • 5
    • 39049097611 scopus 로고    scopus 로고
    • Taurus v. 2004. 12, Synopsys, Inc., 2004.
    • Taurus v. 2004. 12, Synopsys, Inc., 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.