Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (Bulk FinFETS)

IEEE Transactions on Electron Devices

Volumn 53, Issue 3, 2006, Pages 481-487

  Park, Tai Su ^a   Cho, Hye Jin ^b   Choe, Jeong Dong ^b   Han, Sang Yeon ^b   Park, Donggun ^b   Kim, Kinam ^b   Yoon, Euijoon ^a   Lee, Jong Ho ^c  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Kyungpook National University   (South Korea)

Author keywords

Body tied; Bulk FinFET; CMOS fin body; SRAM cell; Static noise margin (SNM); Triple gate (TG)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ETCHING; GATES (TRANSISTOR); MOSFET DEVICES; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SPURIOUS SIGNAL NOISE;

BODY-TIED TRIPLE-GATE; FABRICATION PROCESS; FIN BODY; OPERATIONAL TRANSISTOR; OPTIMIZED CONTROL DEVICES; STATIC NOISE MARGIN (SNM); STATIC RANDOM ACCESS STORAGE CELL;

STATIC RANDOM ACCESS STORAGE;

EID: 33244495722     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.864392     Document Type: Article

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