Impact of local interconnects on timing and power in a high performance microprocessor

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2010, Pages 145-152

  Shelar, Rupesh S ^a   Patyra, Marek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CAD; Delay; Interconnects; Microprocessor; Power

Indexed keywords

45NM TECHNOLOGY; DATA PATHS; DESIGN STYLES; EMPIRICAL STUDIES; HIGH-PERFORMANCE DESIGN; HIGH-PERFORMANCE MICROPROCESSORS; LOCAL INTERCONNECTS; MICROPROCESSOR CORE; NANOMETER TECHNOLOGY; ROUTABILITY; STRUCTURED DATA;

MICROPROCESSOR CHIPS; SYNTHESIS (CHEMICAL); TIME MEASUREMENT; TIMING CIRCUITS; VLSI CIRCUITS;

DESIGN;

EID: 77952263508     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1735023.1735060     Document Type: Conference Paper

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