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Volumn , Issue , 2003, Pages 696-701

Physical synthesis methodology for high performance microprocessors

Author keywords

High Performance; Microprocessors; Synthesis

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; POWER ELECTRONICS; SILICON ON INSULATOR TECHNOLOGY;

EID: 0042134656     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.776009     Document Type: Conference Paper
Times cited : (16)

References (15)
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  • 2
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  • 3
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    • Gradient-based optimization of custom circuits using a static-timing formulation
    • June, IEEE Computer Society Press
    • CONN, A. R. ET AL.. Gradient-based optimization of custom circuits using a static-timing formulation. In Proc. ACM/IEEE Design Automation Conference (June 1999), IEEE Computer Society Press.
    • (1999) Proc. ACM/IEEE Design Automation Conference
    • Conn, A.R.1
  • 6
    • 0031359191 scopus 로고    scopus 로고
    • An integrated placement and synthesis approach for timing closure of PowerPC microprocessors
    • HOJAT, S., AND VILLARUBIA, P. An integrated placement and synthesis approach for timing closure of PowerPC microprocessors. Proc. International Conf. Computer Design (ICCD) (1997), 206-210.
    • (1997) Proc. International Conf. Computer Design (ICCD) , pp. 206-210
    • Hojat, S.1    Villarubia, P.2
  • 7
    • 0032681122 scopus 로고    scopus 로고
    • Harmony: Static noise analysis of deep submicron digital integrated circuits
    • K.L.SHEPARD, V.NARAYANAN, AND R.ROSE. Harmony: Static noise analysis of deep submicron digital integrated circuits. IEEE Transactions on Computer-Aided Design 18, 8 (1999), 1132-1150.
    • (1999) IEEE Transactions on Computer-Aided Design , vol.18 , Issue.8 , pp. 1132-1150
    • Shepard, K.L.1    Narayanan, V.2    Rose, R.3
  • 8
    • 0003254358 scopus 로고    scopus 로고
    • Continuous optimizations in synthesis: The discretization problem
    • KUDVA, P. Continuous optimizations in synthesis: The discretization problem. In International Workshop in Logic Synthesis (1998), pp. 188-191.
    • (1998) International Workshop in Logic Synthesis , pp. 188-191
    • Kudva, P.1
  • 11
    • 0033345381 scopus 로고    scopus 로고
    • High performance 0.18 mm SOI CMOS technology
    • IEEE Computer Society Press
    • LEOBANDUNG, E. ET AL.. High performance 0.18 mm SOI CMOS technology. In IEEE IEDM Technical Digest (1999), IEEE Computer Society Press, pp. 679-682.
    • (1999) IEEE IEDM Technical Digest , pp. 679-682
    • Leobandung, E.1
  • 12
    • 0030189111 scopus 로고    scopus 로고
    • Booledozer: Logic synthesis for ASICs
    • STOK, L. ET AL. Booledozer: Logic synthesis for ASICs. IBM Journal of Research and Development 40, 4 (2001), 407-430.
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  • 15
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    • The circuit and physical design for the power4 microprocessor
    • WARNOCK, J. D. ET AL. The circuit and physical design for the power4 microprocessor. IBM Journal of Research and Development 46, 1 (2002), 27-53.
    • (2002) IBM Journal of Research and Development , vol.46 , Issue.1 , pp. 27-53
    • Warnock, J.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.