Techniques for effective distributed physical synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 859-864

  Mang, Freddy Y C ^a   Hou, Wenting ^a   Ho, Pei Hsin ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Distributed physical synthesis; Partitioning; Time budgeting

Indexed keywords

DISTRIBUTED PHYSICAL SYNTHESIS; PARTITIONING; TIME BUDGETING;

CONTROL SYSTEMS; MATHEMATICAL TECHNIQUES; SCHEDULING;

AUTOMATION;

EID: 34547268009     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375284     Document Type: Conference Paper

References (12)

1. C.J. Alpert, J. Hu, S.S. Sapatnekar and C.N. Sze, Accurate estimation of global buffer delay within a floorplan. ICCAD, pp. 706-711, 2004.
2. H. Chen, C.-K. Cheng, N.-C. Chou and A.B. Kahng, An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering. DAC, pp. 794-799, 2003.
3. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, A High-Quality Mixed-Size Analytical Placer Considering Preplaced Blocks and Density Constraints, ICCAD, pp. 187-192, 2006.
4. Y. Cheon and D.F. Wong, Design Hierarchy Guided Multilevel Circuit Partitioning. TCAD, Volume 22, Issue 4, pp. 420-427, 2003.
5. C.M. Fiduccia and R.M. Mattheyses. A linear time heuristic for improving network partitions. DAC, pp. 175-181, 1982.
6. B. Hu and M. Marek-Sadowska, Wire Length Prediction based Clustering and its Application in Placement.
7. A.B. Kahng, S. Reda, and Q. Wang. Aplace: A general analytic placement framework. ISPD, pp. 233-235, 2005.
8. S.K. Karandikar and S.S. Sapatnekar, Fast comparisons of circuit implementations. IEEE Trans. VLSI Syst. 13(12), 05.
9. G. Karypis, R. Aggarwal, V. Kumar and S. Sheckhar, Multilevel hypergraph partitioning: Application in VLSI domain. DAC, pp. 526-529, 1997.
10. B. Kernighan and S. Lin. An efficient heuristic procedure for partitioning of electrical circuits. Bell System Technical Journal, vol. 49, no. 2, pp. 291-307, 1970.
11. P. Spindler and F.M. Johannes. Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model. ICCAD, pp. 179-186, 2006.
12. I. Sutherland, B. Sproull and D. Harris. Logical effort: designing fast CMOS circuits. Morgan Kaufmann Publishers Inc., 1999.