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Volumn , Issue , 2008, Pages 93-100

Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closuret

Author keywords

[No Author keywords available]

Indexed keywords

ARC COSTS; BENEFITS AND COSTS; BUFFER INSERTIONS; CELL MOVEMENTS; CELL REPLICATIONS; COST FLOWS; CRITICAL PATH DELAYS; CURRENT TECHNIQUES; INCREMENTAL PLACEMENTS; MULTIPLE CIRCUITS; NETWORK FLOW PROBLEMS; NETWORK GRAPHS; PHYSICAL SYNTHESES; SEQUENTIAL APPROACHES; TWO TYPES;

EID: 57849097543     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681557     Document Type: Conference Paper
Times cited : (8)

References (16)
  • 1
    • 46149121212 scopus 로고
    • A Network Simplex Algorithm with O(n) Consecutive Degenerate Pivots
    • R. Ahuja, et al., "A Network Simplex Algorithm with O(n) Consecutive Degenerate Pivots", Operations Research Letters (ORL), pp. 1417-1436, 1995.
    • (1995) Operations Research Letters (ORL) , pp. 1417-1436
    • Ahuja, R.1
  • 3
    • 0031335168 scopus 로고    scopus 로고
    • Gate sizing for constrained delay/power/orea optimization
    • O. Coudert,"Gate sizing for constrained delay/power/orea optimization", IEEE Trans. VLSI, vol. 5, no. 4, pp. 465-472, 1997.
    • (1997) IEEE Trans. VLSI , vol.5 , Issue.4 , pp. 465-472
    • Coudert, O.1
  • 5
    • 46149124374 scopus 로고    scopus 로고
    • A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs
    • S. Dutt, H. Ren, F. Yuan and V. Suthar, "A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs", ICCAD'06, pp. 375-382, 2006.
    • (2006) ICCAD'06 , pp. 375-382
    • Dutt, S.1    Ren, H.2    Yuan, F.3    Suthar, V.4
  • 6
    • 0022231945 scopus 로고
    • Tilos: A posynomial programming approach to transistor sizing
    • J. Fishburn and A. Dunlop, "Tilos: A posynomial programming approach to transistor sizing," ICCAD'85, pp. 326-328, 1985.
    • (1985) ICCAD'85 , pp. 326-328
    • Fishburn, J.1    Dunlop, A.2
  • 7
    • 34547315715 scopus 로고    scopus 로고
    • Gate Sizing For Cell Library-Based Designs
    • S. Hu, M. Ketkary and J. Hu, "Gate Sizing For Cell Library-Based Designs," DAC'07, pp. 847-852, 2007.
    • (2007) DAC'07 , pp. 847-852
    • Hu, S.1    Ketkary, M.2    Hu, J.3
  • 8
    • 0032303080 scopus 로고    scopus 로고
    • Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization
    • Y. Jiang, et al., "Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization", IEEE Trans. VLSI, Vol. 6, No. 4, pp. 625-633, 1998.
    • (1998) IEEE Trans. VLSI , vol.6 , Issue.4 , pp. 625-633
    • Jiang, Y.1
  • 9
    • 0028565174 scopus 로고
    • A Methodology and Algorithms for Post-Placement Delay Optimization
    • L. Kannan, P. Suaris and H. Fang, "A Methodology and Algorithms for Post-Placement Delay Optimization", DAC'94, pp. 327 - 332, 1994.
    • (1994) DAC'94 , pp. 327-332
    • Kannan, L.1    Suaris, P.2    Fang, H.3
  • 10
    • 0032640670 scopus 로고    scopus 로고
    • A solution approach to the fixed charge network flow problem using a dynamic slope scaling procedure
    • D. Kim, and P. Pardalos, "A solution approach to the fixed charge network flow problem using a dynamic slope scaling procedure", ORL, pp. 195-203, 1999.
    • (1999) ORL , pp. 195-203
    • Kim, D.1    Pardalos, P.2
  • 11
    • 0032304661 scopus 로고    scopus 로고
    • ICCD'98
    • A. Lu, H. Eisenmann and G. Stenz, Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization", ICCD'98 pp. 616, 1998.
    • (1998) , pp. 616
    • Lu, A.1    Eisenmann, H.2    Stenz, G.3
  • 14
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree network for minimal Elmore delay
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree network for minimal Elmore delay," Proc. IEEE Int. Symp. Circuits Syst., pp. 865-868, 1990.
    • (1990) Proc. IEEE Int. Symp. Circuits Syst , pp. 865-868
    • van Ginneken, L.P.P.P.1
  • 15
    • 0348040118 scopus 로고    scopus 로고
    • Incremental placement for timing optimization
    • C. Wonjoon, K. Bazargan, "Incremental placement for timing optimization", ICCAD'03, pp. 463-466, 2003.
    • (2003) ICCAD'03 , pp. 463-466
    • Wonjoon, C.1    Bazargan, K.2
  • 16
    • 0036916522 scopus 로고    scopus 로고
    • Timing-driven placement using design hierarchy guided constraint generation
    • Y. Xiaojian, C. Bo-Kyung and M. Sarrafzadeh, "Timing-driven placement using design hierarchy guided constraint generation", ICCAD, pp. 177-180, 2002.
    • (2002) ICCAD , pp. 177-180
    • Xiaojian, Y.1    Bo-Kyung, C.2    Sarrafzadeh, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.