Logical effort model extension to propagation delay representation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 9, 2006, Pages 1677-1684

  Lasbouygues, Benoit ^b   Engels, Sylvain ^b   Wilson, Robin ^a,b   Maurine, Philippe ^c   Azémard, Nadine ^c   Auvergne, Daniel ^c  

^a IEEE

^b STMICROELECTRONICS   (France)

^c LIRMM   (France)

Author keywords

Deep submicron meter; Modeling; Timing analysis

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; FORMAL LOGIC; MOTION PLANNING;

DEEP-SUBMICRON METER; PROPAGATION DELAY; TIMING ANALYSIS; TRANSITION TIME;

DELAY CIRCUITS;

EID: 33748094635     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.857400     Document Type: Article

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