Post-layout logic duplication for synthesis of Domino circuits with complex gates

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 260-265

  Cao, Aiqun ^a   Lu, Ruibing ^a   Koh, Cheng Kok ^b  

^a SYNOPSYS INC   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; LOGIC SYNTHESIS; TIMING CIRCUITS;

ACCURATE TIMING; COMPLEX GATES; DOMINO CIRCUIT; LOGIC DUPLICATION; RE-CONVERGENT PATHS; TECHNOLOGY MAPPING;

COMPUTER CIRCUITS;

EID: 33750983553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120845     Document Type: Conference Paper

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