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Volumn 14, Issue 11, 2006, Pages 1276-1281

Logic Gates as Repeaters (LGR) for area-efficient timing optimization

Author keywords

Delay; Interconnect; Logic; Repeaters; Timing optimization

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INSERTION LOSSES; LOGIC DESIGN; OPTIMIZATION; TELECOMMUNICATION REPEATERS; TIMING JITTER; VLSI CIRCUITS;

EID: 33845535920     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.886400     Document Type: Article
Times cited : (6)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.