ISPD2009 clock network synthesis contest

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2009, Pages 149-150

  Sze, C N ^a   Restle, Phillip ^b   Nam, Gi Joon ^a   Alpert, Charles ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Benchmarks; Clock network synthesis; Physical design; VLSI

Indexed keywords

BENCHMARK SUITES; BENCHMARKS; CLOCK DISTRIBUTION; CLOCK NETWORK SYNTHESIS; DESIGN CHALLENGES; INDUSTRIAL DESIGN; LEADING EDGE; OBJECTIVE FUNCTIONS; PHYSICAL DESIGN; POWER METRICS; PROBLEM FORMULATION; REAL-WORLD; RESEARCH COMMUNITIES; VLSI; VLSI DESIGN;

PRODUCT DESIGN;

ELECTRIC CLOCKS;

EID: 70349113490     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1514932.1514965     Document Type: Conference Paper

References (2)

1. C. Alpert, D. Mehta, and S. Sapatnekar. Handbook of Algorithms for Physical Automation. CRC Press, 2007.
2. N. Sherwani. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, 3rd edition, 1998.